Patents by Inventor Yun Wang

Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190157387
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Application
    Filed: February 27, 2018
    Publication date: May 23, 2019
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Publication number: 20190157409
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Application
    Filed: January 30, 2018
    Publication date: May 23, 2019
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Publication number: 20190156332
    Abstract: An example operation may include one or more of identifying a newly proposed transaction of a blockchain, initiating a consensus operation to determine whether to authorize the newly proposed transaction, retrieving a key-value pair identified from a previous transaction, comparing an index value associated with the key-value pair of the previous transaction to an index value associated with a key-value pair of the newly proposed transaction, and providing an affirmative consensus to accept the newly proposed transaction in the blockchain when the index value associated with the key-value pair of the previous transaction is contiguously sequential with the index value associated with the key-value pair of the newly proposed transaction.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Konstantinos Christidis, Nitin Gaur, Yun Wang
  • Publication number: 20190148537
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure and an S/D contact structure formed over the fin structure. The FinFET device structure also includes an S/D conductive plug formed over the S/D contact structure, and the S/D conductive plug includes a first barrier layer and a first conductive layer. The FinFET device structure includes a gate contact structure formed over the gate structure, and the gate contact structure includes a second barrier layer and a second conductive layer. The FinFET device structure includes a first isolation layer surrounding the S/D conductive plug, and the first barrier layer is between the first isolation layer and the first conductive layer. A second isolation layer surrounding the gate contact structure, and the second barrier layer is between the second isolation layer and the second conductive layer.
    Type: Application
    Filed: April 27, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Huai CHANG, Chao-Hsun WANG, Kuo-Yi CHAO, Mei-Yun WANG
  • Publication number: 20190146357
    Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.
    Type: Application
    Filed: April 27, 2018
    Publication date: May 16, 2019
    Inventors: Wen-Yun WANG, Hua-Tai LIN, Chia-Chu LIU
  • Publication number: 20190148225
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate structure over a fin structure. The method also includes forming an S/D contact structure over a S/D structure and depositing a protection layer over the S/D contact structure. The portion layer and the S/D contact structure are made of different materials. The method further includes forming an etching stop layer over the protection layer and forming a dielectric layer over the etching stop layer. The method includes forming a first recess through the dielectric layer and the etching stop layer to expose the protection layer and forming an S/D conductive plug in the first recess. The S/D conductive plug includes a barrier layer directly on the protection layer, and the protection layer and the barrier layer are made of different materials.
    Type: Application
    Filed: September 7, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yuan CHEN, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Patent number: 10289465
    Abstract: A computer system may encounter an error and receive information regarding the error and the user. The system may use information about the user to generate a message generation profile for the user. The system may use the message generation profile and the information about the error to generate a user-tailored message. The system may monitor the reaction of the user to an error message, and consider the information associated with the reaction when generating user-tailored error messages, subsequently.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Seth M. Packham, Aaron J. Quirk, Lee J. Reamsnyder, Yun Wang
  • Publication number: 20190133866
    Abstract: The present disclosure provides a method for controlling an exoskeleton robot. The method comprises checking that a first signal is triggered by a first button, checking a tilt angle after the first signal is triggered, setting an action based on the tilt angle, and executing the action to move the exoskeleton robot. The first signal indicates to change the exoskeleton robot from a standing posture to another posture, and the tilt angle is a leaning-forward angle of a waist assembly of the exoskeleton robot relative to a line vertical to ground. The method utilizes the tilt angle to judge the intent of the user, and thus can simplify the controlling buttons to one or two buttons. Further, the controlling method also monitors the tilt angle to choose a suitable action.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: YI-JENG TSAI, CHIA-EN HUANG, MING-CHANG TENG, TING-YUN WANG
  • Publication number: 20190138909
    Abstract: A method for encoding and storing text information using DNA as a storage medium, a decoding method therefor and an application thereof. The method for using DNA to store text information comprises: encoding characters into computer binary digits by means of encoding, and converting the binary digits into DNA sequences by means of transcoding; and artificially synthesizing the DNA sequences encoded with character information, positioning the characters by means of a designed ligation adapter, and assembling the DNA sequences encoded with the character information according to a pre-set order. The method for using DNA to store text information has the advantages of a small storage volume, a large storage capacity, a strong stability and low maintenance costs.
    Type: Application
    Filed: May 4, 2016
    Publication date: May 9, 2019
    Inventors: Yue SHEN, Tai CHEN, Longying LIU, Shihong CHEN, Yun WANG, Huanming YANG
  • Patent number: 10283403
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Publication number: 20190131644
    Abstract: Disclosed here is a supported catalyst comprising a thermally stable core, wherein the thermally stable core comprises a metal oxide support and nickel disposed in the metal oxide support, wherein the metal oxide support comprises at least one base metal oxide and at least one transition metal oxide or rare earth metal oxide mixed with or dispersed in the base metal oxide. Optionally the supported catalyst can further comprise an electrolyte removing layer coating the thermally stable core and/or an electrolyte repelling layer coating the electrolyte removing layer, wherein the electrolyte removing layer comprises at least one metal oxide, and wherein the electrolyte repelling layer comprises at least one of graphite, metal carbide and metal nitride. Also disclosed is a molten carbonate fuel cell comprising the supported catalyst as a direct internal reforming catalyst.
    Type: Application
    Filed: April 10, 2017
    Publication date: May 2, 2019
    Inventors: Jin-Yun WANG, Mohammad FAROOQUE, Ramakrishnan VENKATARAMAN, Chao-Yi YUH, April CORPUZ
  • Patent number: 10276437
    Abstract: A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Audrey Hsiao-Chiu Hsu, Fu-Kai Yang, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Hsin-Ying Lin
  • Patent number: 10276448
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Patent number: 10272415
    Abstract: The present invention discloses a method for preparing a catalyst, comprising the following steps: (1) taking a noble metal salt solution A, adding a modified alumina support material, stirring until uniform and standing; (2) drying the material obtained in step (1) in a vacuum, and calcining at 500° C.-600° C. for 1-4 hours to obtain a powder material containing the noble metal; (3) mixing the noble metal powder material, an adhesive and other components to be added, and ball-milling to obtain a uniform slurry; (4) preparing a noble metal solution B and adjusting pH to 0.5-1; and (5) mixing the slurry of the step (3) with the noble metal solution B, coating the mixture on a support, drying, and calcining at 500° C.-600° C. for 1-2 hours to obtain the target product. The method for preparing the catalyst of the present invention is simple, the conditions of the preparation process are easy to control and the preparation method has strong practicality.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 30, 2019
    Assignee: Sinocat Environmental Technology Co., Ltd.
    Inventors: Dacheng Li, Yun Li, Yun Wang, Qin Wang, Yongxiang Cheng, Yaoqiang Chen
  • Patent number: 10269621
    Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang, Kuo-Yi Chao
  • Patent number: 10264718
    Abstract: An external-leadwire crimping apparatus is provided by embodiments of the present invention, including: a heating base provided with a heating rod and a temperature sensor; a crimping tool tip which is connected with the heating base and supplied with heat from the heating base, the crimping tool tip being configured to to crimp a leadwire of a flexible printed circuit board onto a printed circuit board assembly, by curing a conductive adhesive after receipt of heat, and the crimping tool tip comprising a crimping tool tip body. The crimping tool tip body is provided with at least one heat dissipation slot on an upper surface thereof, the heat dissipation slot being configured to extend in a thickness direction of the crimping tool tip body and to penetrate therethrough at both ends; and the crimping tool tip body is provided with at least one heat dissipation hole penetrating the thickness direction thereof.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 16, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yusheng Ke, Yanping Li, Jiali Wang, Junjun Liu, Yun Wang, Xinwei Huang
  • Patent number: 10260405
    Abstract: An internal combustion engine has a cylinder configured to combust an air-fuel mixture and expel an exhaust gas and a turbocharger for generating a pressurized airflow to the cylinder. The turbocharger includes a turbine scroll defining an inlet and an outlet, an exhaust gas driven rotating assembly having a turbine wheel disposed inside the turbine scroll, and a waste-gate defining an opening. A first sensor detects turbine outlet pressure. A second sensor detects turbine inlet temperature. A controller determines an effective area of the waste-gate opening and an exhaust gas mass flow-rate. The controller also determines a turbine inlet pressure in response to the detected turbine outlet pressure and the turbine inlet temperature, and the determined waste-gate opening effective area and the exhaust gas mass flow-rate. The controller additionally regulates a supply of fuel to the cylinder corresponding to the pressurized airflow affected by the determined turbine inlet pressure.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 16, 2019
    Assignee: GM Global Technology Operations LLC
    Inventors: Yue-Yun Wang, Martin Suchy, Joerg Bernards
  • Patent number: 10263019
    Abstract: A flexible panel includes a substrate, a first insulating layer, a second insulating layer, a sacrificial layer, and a metal wiring layer. The substrate has an active area, a peripheral area, and an intermediate area. The first insulating layer is in the three areas of the substrate, and the first insulating layer in the intermediate area has a first pattern. The second insulating layer is on the first insulating layer. The second insulating layer in the intermediate area has a first opening extending along a first direction, so that the second insulating layer does not cover the first pattern of the first insulating layer. The sacrificial layer is between the first insulating layer and the second insulating layer in the intermediate area, and does not cover the first pattern of the first insulating layer. The metal wiring layer extends between the active area and the peripheral area.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 16, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Pei-Yun Wang, Cheng-Wei Jiang, Ting-Yu Hsu, Ya-Qin Huang, Hsiang-Yun Hsiao, Chia-Kai Chen
  • Publication number: 20190109041
    Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang, Kuo-Yi Chao
  • Patent number: 10257686
    Abstract: Methods and systems for joining a wireless connection advertisement include connecting to a commissioning device via a wireless point-to-point communication in response to receiving an advertisement broadcast to establish an advertisement-based connection. The commissioning device is configured to manage access to a fabric. The methods and systems also include receiving network credentials from the commissioning device via the wireless point-to-point communication, the network credentials being configured to facilitate connection to a wireless network. Furthermore, the method and systems include connecting to the wireless network using the received network credentials.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 9, 2019
    Assignee: Google LLC
    Inventors: Jay D. Logue, Liang-Yun Wang, Andrew William Stebbins