Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.

Abstract: A method for forming complementary FinFET (CFET) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. In another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. A CFET device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.

Abstract: The application relates to an anti-back-transfer intake structure of a rotating detonation combustion chamber including a Tesla valve communicating with the rotating detonation combustion chamber and arranged at an inlet of the rotating detonation combustion chamber. The Tesla valve includes a casing and a flow passage, the casing is coaxially connected with an outer wall of the rotating detonation combustion chamber, the flow passage is arranged in the casing, and the flow passage has an inlet end for introducing air, and an outlet end connected with an annular passage of the rotating detonation combustion chamber.

Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.

Abstract: Disclosed in the present invention are a peptide compound, an application thereof, and a composition containing the same. Provided in the present invention are a peptide compound, a pharmaceutically acceptable salt thereof, a tautomer thereof, a solvate thereof, a crystal form thereof, or a prodrug thereof. The compound has good stability and good activity.

Abstract: A method for preparing high-toughness heat-resistant aluminum alloy armature material, comprises: heating and melting an aluminum ingot into an aluminum liquid; adding the following elements to the aluminum solution in mass percent: Ce 6-12%, Y 5-9.5%, Zr 0.5-3%, Mg 0.1-2.5%, X 0.15-2.5%, Fe 0.15-0.25%, Mn 0.05-0.15%, and Si 0.1-0.5%; forming an alloy solution and casting same into an alloy ingot; processing the alloy ingot into spherical alloy powder; subjecting the spherical alloy powder to selective laser melting and solidification forming to produce nano-scale Al11Ce3, Al3(Y, Zr), and/or Al3X intermetallic compounds distributed in a net-like skeleton structure in an aluminum matrix. The material of the present disclosure has low density, high-temperature resistance, high energy absorption rate and excellent electrical conductivity, and excellent mechanical properties at room temperature and high temperature.

Abstract: A spiral ultrasonic tomography imaging method and system are provided. The method is to use synchronous rotation of an ultrasonic probe or cyclic switching of emission array elements in the ultrasonic probe under the premise of a uniform displacement of the ultrasonic probe along the Z axis, so that the change trajectory of the positions of emission array elements over time in a three-dimensional space at each ultrasonic emission time is distributed along a spiral line or a curve. During the process of the uniform displacement of the ultrasonic probe along the Z axis, the ultrasonic probe emits ultrasonic waves and receives and collects echo data. The collected echo data is stored and post-processed to realize ultrasonic tomography imaging of an object. The spiral ultrasonic tomography three-dimensional scanning method and the corresponding system realize rapid continuous uninterrupted data acquisition to ensure that higher spatial resolution in the Z-axis direction.

Abstract: The present invention provides a smart wearable device, which is held on an upper body of a wearer by a plurality of contact pad sets, and has a connection unit, a first sensing module, a second sensing module, and an extension unit.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: The application relates to an anti-back-transfer intake structure of a rotating detonation combustion chamber including a Tesla valve communicating with the rotating detonation combustion chamber and arranged at an inlet of the rotating detonation combustion chamber. The Tesla valve includes a casing and a flow passage, the casing is coaxially connected with an outer wall of the rotating detonation combustion chamber, the flow passage is arranged in the casing, and the flow passage has an inlet end for introducing air, and an outlet end connected with an annular passage of the rotating detonation combustion chamber.

Abstract: The present application relates to a pregabalin sustained release composition, comprising: (a) an active ingredient; (b) a matrix-forming agent; (c) a swelling agent; (d) a gelling agent; and optionally a filler. The pregabalin sustained release composition provided in the present application can rapidly swell in volume when exposed to aqueous medium until exceeding the dimeter of human gastric pyloric (13 mm). It thereby prolongs the gastric emptying time to increase the retention time of pregabalin in the stomach and enhances absorption of pregabalin in the small intestine and ascending colon. Moreover, the pregabalin sustained release composition provided herein achieves a sustained release for 24 h, which allows QD (once a day) administration, reduces administration number, and improves patient compliance.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.