Abstract: A damascene structure, such as a conductive line or via, having a liner with a roughened surface between the substrate and the conductive fill and, preferably, a smooth bottom. The substrate underneath the liner may also have a roughened sidewall and smooth bottom. Such a structure provides enhanced adhesion between one or more layers of the damascene structure. The damascene structure may be manufactured by applying a photoresist over a substrate top surface, exposing the photoresist under conditions that create a standing wave in the resist, and developing the photoresist to provide a pattern having the desired roughened or serrated outline. The pattern is transferred into the substrate, the liner is applied over the substrate bottom and sidewalls, and the liner is filled with conductive material. A roughened liner surface may be achieved by applying a partial layer of liner material over the substrate, removing a portion of the partial layer, and repeating the application and removal steps.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.

Abstract: Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.

Abstract: A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.

Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.