Patents by Inventor Yung Cheng Chen

Yung Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240156405
    Abstract: A smart wearable device has a signal calibration function executed by a signal calibration method and applied to a finger, a limb and/or a neck of a user. The smart wearable device includes at least one physiological signal detector, at least one pressure detector and an operation processor. The at least one physiological signal detector is adapted to abut against a detection area of the user for detecting a physiological signal. The at least one pressure detector is disposed around the at least one physiological signal detector and adapted to detect a pressure value of the detection area. The operation processor is electrically connected with the at least one physiological signal detector and the at least one pressure detector. The operation processor is adapted to optimize the physiological signal when the pressure value exceeds a predefined pressure threshold.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 16, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Yung-Chang Lin, Jian-Cheng Liao, Chun-Chih Chen, Sen-Huang Huang, Yen-Min Chang
  • Patent number: 11980864
    Abstract: A method of operating an integrated circuit includes using a first switching device to couple a bio-sensing device to a first signal path, generating, using the bio-sensing device, a bio-sensing signal on the first signal path in response to an electrical characteristic of a sensing film, using a second switching device to couple a temperature-sensing device to a second signal path, and generating, using the temperature-sensing device, a temperature-sensing signal on the second signal path in response to a temperature of the sensing film. The first and second switching devices, the bio-sensing device, the temperature-sensing device, and the sensing film are components of a sensing pixel of a plurality of sensing pixels of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
  • Publication number: 20240153895
    Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 9, 2024
    Inventors: Harry-HakLay CHUANG, Wei-Cheng WU, Chung-Jen HUANG, Yung Chun TU, Chien Lin LIU, Shun-Kuan LIN, Ping-tzu CHEN
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11955370
    Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20240045343
    Abstract: A method includes providing a workpiece to a semiconductor apparatus, the workpiece including a material layer including a first strip having: a first plurality of exposure fields; and a second plurality of exposure fields alternatingly arranged with the first plurality of exposure fields. The method further includes: scanning the first strip along a first scan route from a first side of the workpiece to a second side of the workpiece to generate first topography measurement data; scanning the first strip along a second scan route from the second side to the first side to generate second topography measurement data; and exposing the first plurality of exposure fields and exposing the second plurality of exposure fields according to the first topography measurement data and the second topography measurement data.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: YUNG-YAO LEE, YEH-CHIN WANG, YANG-ANN CHU, YUNG-HSIANG CHEN, YUNG-CHENG CHEN
  • Patent number: 11835866
    Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece including a material layer, wherein the material layer includes a first strip having a first plurality of exposure fields configured to be exposed in a first direction and a second plurality of exposure fields configured to be exposed in a second direction different from the first direction; scanning the first strip along a first scan route in the first direction to generate first topography measurement data; scanning the first strip along a second scan route in the second direction to generate second topography measurement data; and exposing the first plurality of exposure fields according to the first topography measurement data and exposing the second plurality of exposure fields according to the second topography measurement data.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, Yeh-Chin Wang, Yang-Ann Chu, Yung-Hsiang Chen, Yung-Cheng Chen
  • Publication number: 20230324814
    Abstract: An extreme ultra violet (EUV) lithography apparatus includes a light source that generates an EUV light beam, a scanner that receives the light from a junction with the light source and directs the light to a reticle stage, and a debris catcher disposed on a EUV beam path between the light source and the scanner. The debris catcher includes a network membrane including a plurality of nano-fibers.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Inventors: I-Hsiung HUANG, Yung-Cheng CHEN, Tung-Li WU
  • Publication number: 20230152686
    Abstract: Methods for removing haze defects from a photomask or reticle are disclosed. The photomask is placed into a chamber which includes a hydrogen atmosphere. The photomask is then exposed to radiation. The energy from the radiation, together with the hydrogen, causes decomposition of the haze defects. The methods can be practiced on-site and quickly, without the need for wet chemicals or the need to remove the pellicle before cleaning of the photomask. A device for conducting the methods is also disclosed herein.
    Type: Application
    Filed: March 9, 2022
    Publication date: May 18, 2023
    Inventors: I-Hsiung HUANG, Yung-Cheng Chen, Chi-Lun Lu
  • Publication number: 20230085172
    Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece including a material layer, wherein the material layer includes a first strip having a first plurality of exposure fields configured to be exposed in a first direction and a second plurality of exposure fields configured to be exposed in a second direction different from the first direction; scanning the first strip along a first scan route in the first direction to generate first topography measurement data; scanning the first strip along a second scan route in the second direction to generate second topography measurement data; and exposing the first plurality of exposure fields according to the first topography measurement data and exposing the second plurality of exposure fields according to the second topography measurement data.
    Type: Application
    Filed: October 31, 2022
    Publication date: March 16, 2023
    Inventors: YUNG-YAO LEE, YEH-CHIN WANG, YANG-ANN CHU, YUNG-HSIANG CHEN, YUNG-CHENG CHEN
  • Publication number: 20230008957
    Abstract: A photolithography exposure of a photoresist coating on a semiconductor wafer uses an optical projection system to form a latent image. The photolithography exposure further uses a mask with a set of multiple pattern focus (MPF) marks. Each MPF mark of includes features having different critical dimension (CD) sizes. The latent image is developed to form a developed photoresist pattern. Dimension sizes are measured of features of the developed photoresist pattern corresponding to the features of the MPF marks having different CD sizes. A spatial focus map of the photolithography exposure is constructed based on the measured dimension sizes. To determine the focal distance at an MPF mark, ratios or differences may be determined between the measured dimension sizes corresponding to the features of the MPF marks having different CD sizes, and the focal distance at the location of the MFP mark constructed based on the determined ratios or differences.
    Type: Application
    Filed: February 8, 2022
    Publication date: January 12, 2023
    Inventors: I-Hsiung Huang, Yung-Cheng Chen, Tzung-Hua Lin, Feng-Yuan Chang
  • Patent number: 11487210
    Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece comprising a material layer, wherein the material layer includes a plurality of areas extending along a first axis; scanning the workpiece in a first direction along the first axis to generate first topography measurement data; scanning the workpiece in a second direction along the first axis to generate second topography measurement data; and performing an exposure operation on the material layer according to the first topography measurement data and the second topography measurement data.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, Yeh-Chin Wang, Yang-Ann Chu, Yung-Hsiang Chen, Yung-Cheng Chen
  • Publication number: 20210263425
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN
  • Patent number: 11003314
    Abstract: Disclosed herein are systems, methods, and software for implementing enhanced menu presentation technology. In at least one implementation, a user interface to a personal information service is presented by a suitable computing system. The user interface includes a viewing pane and an information panel in which various personal information items may be organized. In response to a selection of any of the personal information items for viewing, content associated with the item is presented in the viewing pane. In addition, in response to an identification of an action group that includes multiple ones of the personal information items, an action menu is presented in at least a portion of a space in the user interface occupied by the viewing pane.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 11, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kutlay Topatan, Poonam G. Hattangady, Yung-Cheng Chen, Jeffrey Feiereisen
  • Patent number: 11003091
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 10725632
    Abstract: Techniques for providing an in-place contextual menu and user interface for email and other information management system triage are provided in which a contextual menu can be overlaid or replace an item on a view screen. The contextual menu can provide action commands specific to the type and state of the items selected in the feature view of the email or other information management system. A single recognized selection input, such as a swipe gesture, selects an item and invokes an in-place contextual menu presenting actions that can be asserted on the selected item. Multiple item selection is available through the same invocation of presenting the in-place contextual menu.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 28, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jeffrey K. Feiereisen, Yung-Cheng Chen, Ryan Thomas Murphy, Eva Britta Karolina Burlin, Michael Anthony Faoro, Kenneth Fern, Michael R. Gow, Chao-Chung Lin, Joseph McLaughlin
  • Publication number: 20200150546
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN
  • Patent number: 10534272
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20190004436
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN