Abstract: In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short channel effect (SCE) between the drain regions and the source region in the NOR flash memory.

Abstract: A method for fabricating a NOR semiconductor memory structure includes: performing a deeply doped source ion implantation process and a lightly doped drain ion implantation process; forming oxide layer walls on two said sides of a gate structure, respectively; performing a pocket implant process with control of an incident angle thereof; and performing a deeply doped drain ion implantation process. Characteristics of the NOR semiconductor memory structure are improved by controllably changing the position of a pocket implant region.

Abstract: A micro electro-mechanical (MEMS) device assembly is provided. The MEMS device assembly includes a first substrate that has a plurality of electronic devices, a plurality of first bonding regions, and a plurality of second bonding regions. The MEMS device assembly also includes a second substrate that is bonded to the first substrate at the plurality of first bonding regions. A third substrate having a recessed region and a plurality of standoff structures is disposed over the second substrate and bonded to the first substrate at the plurality of second bonding regions. The plurality of first bonding regions provide a conductive path between the first substrate and the second substrate and the plurality of the second bonding regions provide a conductive path between the first substrate and the third substrate.

Abstract: The present invention provides a polishing pad. The polishing pad comprises a transparent part and a high molecular weight layer. The transparent part has an uneven side surface and the profile of the uneven side surface is selected from a group consisting of a serrated shape, a wavy shape and a toothed shape. The high molecular weight layer encircles the transparent part.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

Abstract: In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract: A method of manufacturing super-absorbent polymer (SAP) which is powdery, insoluble in water, and able to absorb water, blood and urine with slight soluble substances. The method includes at least the following steps: mixing a monomer solution having at least 50 mol % of neutralized acrylic acid with polymerization initiators to synthesize a sticky precursor, wherein the monomer can be selected from acrylic acid, methacrylic acid, 2-acrylamido-2-methyl-propane sulfonic acid, or the mixtures thereof; mixing high hydrophilic epoxy compounds and polymerization initiators with the precursor and producing a gel via UV cross-linking; drying the gel at temperature of 100 to 250° C. to obtain a polymer; grinding and screening the polymer into constant particle size; coating the polymer with surface cross-linking agents; heating the polymer at temperature of 80 to 230° C.; and adding powdery inert inorganic salts into the polymer.

Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract: A testing device for portable electronic devices includes a processor storing test programs corresponding to various portable electronic devices, a control module connected to the processor, and a testing apparatus connected to the control module and connecting to tested portable electronic devices. The processor directs the control module and the testing apparatus to test portable electronic devices according to predetermined test programs in a main control mode, and the control module cooperates with the testing apparatus to test portable electronic devices and directs the processor to select test programs according to the tested portable electronic device in a subsidiary control mode.

Abstract: An LED flat lamp including a housing with a light-emitting area at the bottom thereof. The internal side thereof undergoes a reflexion treatment. At least one LED is disposed within the housing. A power connector is extended from the LED to the outside. The LED is installed on a circuit board. A light guide plate is installed at one side of the LED within the housing. The light exit side of the light guide plate is provided with a microstructure for a uniform light exit. Moreover, an optical film unit is attached to the bottom of the light guide plate such that the light-emitting area of the housing is covered with the optical film unit. The optical film unit consists of one or several brightness enhancement films and one or several diffusers. In this way, the problem of glaring light directly emitted by the prior art is resolved. The LED flat lamp in accordance with the invention can emit a non-glaring light and can be modularized into a standardized product.

Abstract: A process provides, if a language interpreter candidate is a beginning level language interpreter candidate, a preliminary self-assessment and a language proficiency test. Further, the process provides, if the language interpreter has a predetermined amount of entry level language interpreter experience or has completed beginning level language interpreter requirements, an interpreter skills assessment test. Finally, the process provides, if the language interpreter candidate has a predetermined amount of professional level language interpreter experience, a predetermined amount of training in a subject matter field associated with the subject matter skill set, or has passed the interpreter skills assessment test, a subject matter skill set language interpretation certification test.

Abstract: A process provides a screening of a candidate on a prerequisite. Further, the process provides a written examination to a qualified candidate. The qualified candidate passes the screening. In addition, the process provides an oral examination to the qualified candidate if the qualified candidate passes the written examination. The process also provides examination results to the qualified candidate. Finally, the process provides certification to the qualified candidate if the qualified candidate passes both the written examination and the oral examination.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Abstract: An LED flat lamp including a housing with a light-emitting area at the bottom thereof. The internal side thereof undergoes a reflexion treatment. At least one LED is disposed within the housing. A power connector is extended from the LED to the outside. The LED is installed on a circuit board. A light guide plate is installed at one side of the LED within the housing. The light exit side of the light guide plate is provided with a microstructure for a uniform light exit. Moreover, an optical film unit is attached to the bottom of the light guide plate such that the light-emitting area of the housing is covered with the optical film unit. The optical film unit consists of one or several brightness enhancement films and one or several diffusers. In this way, the problem of glaring light directly emitted by the prior art is resolved. The LED flat lamp in accordance with the invention can emit a non-glaring light and can be modularized into a standardized product.

Abstract: A sinter-hardening powder can yield a sintered compact with high strength, high hardness, and high density. A raw powder for sintering includes Fe as its primary component and also comprising 0.1-0.8 wt % C, 5.0-12.0 wt % Ni, 0.1-2.0 wt % Cr, and 0.1-2.0 wt % Mo, wherein the mean particle size of the raw powder for sintering is 20 ?m or less. The sintered and tempered compact, without any quenching treatment, has high hardness, high strength, high density, and good ductility.

Abstract: A sinter-hardening raw powder can yield a press-and-sinter compact with high hardness. The raw powder for sintering includes Fe as its primary component and also includes 0.3-0.8 wt % C, 5.0-12.0 wt % Ni, 1.0-5.0 wt % Cr, and 0.1-2.0 wt % Mo, wherein the mean particle size of the raw powder for sintering is between 50 and 100 ?m. The sintered and tempered compact, without any quenching treatment, has high hardness.