Abstract: A method for reading data in a nonvolatile memory at a power-on stage is provided and includes the following steps. Firstly, the data are read through a reference voltage. Next, a failure number is counted when reading the data has a fail result. Next, the reference voltage is adjusted when the failure number reaches a predetermined number. The effect effectively and exactly reading configuration information at a power-on stage is accomplished through the method.

Abstract: A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage.

Abstract: An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a pre-charge time to make the target word line be charged to the target voltage. The initial enable voltage is higher than the target voltage. The pre-charge time corresponds to the initial enable voltage and the target voltage.

Abstract: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.

Abstract: A word line boost circuit includes a first pump circuit, a first transistor, a voltage detection circuit and a second pump circuit. The first pump circuit provides a gate boosted signal according to an address transfer detection (ATD) signal. The first transistor has a control terminal for receiving the gate boosted signal and a second terminal coupled to a target word line. The voltage detection circuit is for detecting a voltage level of the gate boosted signal and accordingly outputting a detection signal. The second pump circuit is for outputting a boost signal to a first terminal of the first transistor according to a voltage level of the detection signal. The boost signal boosts the target word line via the turned-on first transistor.

Abstract: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.

Abstract: A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node when selected, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.

Abstract: A voltage regulation unit with a Zener diode receives a driving voltage outputted from a charge pump and controls a level of the driving voltage to regulate the driving voltage. The voltage regulation unit includes a current mapping unit, a Zener diode and a biasing unit. The current mapping unit receives the driving voltage and generates first and second current signals at master and slave current ends according to the driving voltage, respectively. The diode receives the first current signal and controls the level of the driving voltage to be substantially equal to a predetermined voltage level. The biasing unit receives the second current signal, judges whether the level of the driving voltage reaches the predetermined voltage level according to the second current signal, and outputs a control signal, which is fed back to the charge pump to control the charge pump to generate the driving voltage.

Abstract: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL?K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Abstract: A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the first set of selected bit lines to corresponding members of a second set of selected bit lines. The second set of selected bit lines, having an initial charge transferred from the first set, is then pre-charged to the pre-charge voltage. The data from the cells coupled to the second set of selected bit lines it is then sensed. In embodiments described herein, the read operation occurs in a burst read mode, where a volume of data having consecutive addresses is read.

Abstract: An accessing method for a charge trapping memory including memory cells and tracking cells for storing expected data. The method includes the following steps. In a specific time first, the expected data is written into the tracking cells and the memory cells are not being programmed, read or erased. Next, the data stored in the tracking cells is sensed as read data according to a present reference current. Then, the present reference current is adjusted to an adjusted reference current according to a difference between the read data and the expected data so that the data stored in tracking cells is sensed as corresponding with the expected data according to the adjusted reference current. Thereafter, the memory cells are read according to the adjusted reference current.

Abstract: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than the first PV level of the targeted programmed state such that at least one bit of them has a Vt level larger than a second PV level corresponding to a targeted programmed state, wherein the second PV level of the targeted programmed state is larger than the corresponding first PV level; and programming only the bits of the memory with a Vt level lower than the first PV level of the targeted programmed state such that each of them has a Vt level larger than the first PV level of the targeted programmed state.

Abstract: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than the first PV level of the targeted programmed state such that at least one bit of them has a Vt level larger than a second PV level corresponding to a targeted programmed state, wherein the second PV level of the targeted programmed state is larger than the corresponding first PV level; and programming only the bits of the memory with a Vt level lower than the first PV level of the targeted programmed state such that each of them has a Vt level larger than the first PV level of the targeted programmed state.

Abstract: A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node when selected, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node.

Abstract: An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a pre-charge time to make the target word line be charged to the target voltage. The initial enable voltage is higher than the target voltage. The pre-charge time corresponds to the initial enable voltage and the target voltage.

Abstract: A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the first set of selected bit lines to corresponding members of a second set of selected bit lines. The second set of selected bit lines, having an initial charge transferred from the first set, is then pre-charged to the pre-charge voltage. The data from the cells coupled to the second set of selected bit lines it is then sensed. In embodiments described herein, the read operation occurs in a burst read mode, where a volume of data having consecutive addresses is read.

Abstract: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.

Abstract: A voltage regulation unit with a Zener diode receives a driving voltage outputted from a charge pump and controls a level of the driving voltage to regulate the driving voltage. The voltage regulation unit includes a current mapping unit, a Zener diode and a biasing unit. The current mapping unit receives the driving voltage and generates first and second current signals at master and slave current ends according to the driving voltage, respectively. The diode receives the first current signal and controls the level of the driving voltage to be substantially equal to a predetermined voltage level. The biasing unit receives the second current signal, judges whether the level of the driving voltage reaches the predetermined voltage level according to the second current signal, and outputs a control signal, which is fed back to the charge pump to control the charge pump to generate the driving voltage.