Abstract: A voltage regulation unit with a Zener diode receives a driving voltage outputted from a charge pump and controls a level of the driving voltage to regulate the driving voltage. The voltage regulation unit includes a current mapping unit, a Zener diode and a biasing unit. The current mapping unit receives the driving voltage and generates first and second current signals at master and slave current ends according to the driving voltage, respectively. The diode receives the first current signal and controls the level of the driving voltage to be substantially equal to a predetermined voltage level. The biasing unit receives the second current signal, judges whether the level of the driving voltage reaches the predetermined voltage level according to the second current signal, and outputs a control signal, which is fed back to the charge pump to control the charge pump to generate the driving voltage.

Abstract: Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.

Abstract: A memory circuit that generates a positive temperature correlated clock frequency is described. One embodiment includes a voltage reference having a voltage determined at least in part by a diode or transistor having a negative temperature coefficient. A clock generator generates a clock having a frequency that is based at least in part on the voltage reference voltage so that the clock frequency has a positive temperature correlation. A memory charge pump is enabled at least in part by the clock.

Abstract: Various embodiments address the problem of efficiently reading data from nonvolatile memory. Nonvolatile memory circuit, method, and manufacturing method embodiments relate to a virtual ground array of nonvolatile memory cells which are read by precharging the drains of multiple nonvolatile memory cells and measuring the resulting currents. Power consumption and read margins are improved by reading multiple cells. Unnecessary bit line precharging can be avoided.

Abstract: An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.

Abstract: A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired in the sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. In this way, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.

Abstract: A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired using in sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. Thereby, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.