Patents by Inventor Yung-Hsiang Chen
Yung-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12142640Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.Type: GrantFiled: September 22, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shan-Mei Liao, Yung-Hsiang Chan, Yao-Teng Chuang, Jian-Hao Chen, Kuo-Feng Yu
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Publication number: 20240355684Abstract: A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.Type: ApplicationFiled: May 4, 2023Publication date: October 24, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chih Feng Sung, Wei Han Huang, Ming-Jui Tsai, Yu Chi Chen, Yung-Hsiang Chang, Chun-Lin Lu, Shih-Ping Lee
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Patent number: 12124293Abstract: An electronic device is provided. The electronic device includes a first body with a base and a movable member, a second body, a lifting member, and a linkage mechanism. The movable member is located on an upper surface of the base and includes a first side and a second side. The first side is pivotally connected to the base. The second body is pivotally connected to the second side by using a first rotary shaft. The lifting member is pivotally connected to the movable member by using a second rotary shaft. The linkage mechanism is disposed on the movable member, is linked to the second body by using the first rotary shaft, and drives the lifting member to rotate by using the second rotary shaft. When the second body is opened upward, an air outlet on a rear side of the first body is prevented from being covered.Type: GrantFiled: February 22, 2022Date of Patent: October 22, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Yung-Hsiang Chen, Li-Wei Hung
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Publication number: 20240347571Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Inventors: Yung-Hsiang CHEN, Yu-Lung YEH, Yen-Hsiu CHEN, Bo-Chang SU, Cheng-Hsien CHEN
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Publication number: 20240332382Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: Yung-Hsiang Chan, Shan-Mei Liao, Wen-Hung Huang, Jian-Hao Chen, Kuo-Feng Yu, Mei-Yun Wang
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Publication number: 20240321626Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.Type: ApplicationFiled: May 29, 2024Publication date: September 26, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Yang Du, Yung-Fong Lin, Tsung-Hsiang Lin, Yu-Chieh Chou, Cheng-Tao Chou, Yi-Chun Lu, Chun-Hsu Chen
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Publication number: 20240297261Abstract: A semiconductor device includes a substrate, a buffer layer, a gradient layer, an active layer, a window layer, and an optical filtering layer. The substrate includes a first element and a second element. The buffer layer is disposed on the substrate. The gradient layer is formed on the buffer layer, and includes sublayers. Each sublayer includes the first, second, and third elements. For each sublayer, a lattice constant thereof is adjusted by changing a ratio of the second element to the third element. The active layer is formed on the gradient layer, and includes the first, second, and third elements. The window layer is formed on the active layer. The optical filtering layer includes the first, second, and third elements, and is formed on the window layer to block a portion of light having a wavelength in a predetermined wavelength range.Type: ApplicationFiled: March 1, 2024Publication date: September 5, 2024Inventors: Hung-Wen HUANG, Yung-Chao CHEN, Yi-Hsiang WANG, Wei LIN
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Patent number: 12080604Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.Type: GrantFiled: July 31, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
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Publication number: 20240268120Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first circuit layer, a memory array structure, a bonding layer, a second circuit layer, and a second substrate. The first circuit layer is disposed on the first substrate. The memory array structure is disposed on the first circuit layer. The bonding layer is disposed on the memory array structure. The second circuit layer is disposed on the bonding layer. The second substrate is disposed on the second circuit layer.Type: ApplicationFiled: February 8, 2023Publication date: August 8, 2024Inventors: Yung-Hsiang CHEN, Tao-Cheng LU, Yao-Wen CHANG
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Patent number: 12051180Abstract: A method for generating images with high dynamic range (HDR) based on multiple images captured at different aperture values, under different conditions, or at different shutter speeds is applied in a device. The method inputs the original multiple images into a predetermined model and aligns the multiple images. The method further confirms object images that need to be attended among multiple aligned images and obtains a merge weighting for each of the object images, and merges the images for a generated HDR according to the merge weighting of each image. The device utilizing the method is also disclosed.Type: GrantFiled: April 29, 2021Date of Patent: July 30, 2024Assignee: Chiun Mai Communication Systems, Inc.Inventors: Sheng-Yeh Chen, Yung-Yu Chuang, Tzu-Kuei Huang, Nai-Sheng Syu, Yu-Ching Wang, Ting-Hao Chung, Chun-Hsiang Huang
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Patent number: 12046615Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.Type: GrantFiled: March 4, 2021Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Bo-Chang Su, Cheng-Hsien Chen
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Publication number: 20240241337Abstract: An optical element driving mechanism is provided, and includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect an optical element and is movable relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion in a first axis. The driving assembly is arranged along a second axis, and the second axis is perpendicular to the first axis.Type: ApplicationFiled: January 16, 2024Publication date: July 18, 2024Inventors: Yung-Yun CHEN, Jui-Che MENG, Tso-Hsiang WU, Ko-Lun CHAO
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Publication number: 20240241426Abstract: An optical element driving mechanism is provided, and includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect an optical element and is movable relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion in a first axis.Type: ApplicationFiled: January 16, 2024Publication date: July 18, 2024Inventors: Yung-Yun CHEN, Jui-Che MENG, Tso-Hsiang WU, Ko-Lun CHAO
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Publication number: 20240234589Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.Type: ApplicationFiled: March 27, 2024Publication date: July 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
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Patent number: 12001248Abstract: A hinge structure applied to an electronic device having a first component and a second component is provided. The hinge structure includes a torque hinge and a one-way pivoting mechanism. The torque hinge includes a first base and a first rotation element. The first base connects to the first component. The first rotation element rotatably connects to the first base. The second component pivotally connects to the first rotation element through the one-way pivoting mechanism.Type: GrantFiled: May 28, 2021Date of Patent: June 4, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Tsung-Ju Chiang, Marco Da Ros, Yung-Hsiang Chen, Li Wei Hung
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Patent number: 11988625Abstract: A capacitive biosensor is provided. The capacitive biosensor includes: a transistor, an interconnect structure on the transistor, and a passivation layer on the interconnect structure. The interconnect structure includes a first metal structure on the transistor, a second metal structure on the first metal structure, and a third metal structure on the second metal structure. The third metal structure includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The passivation has an opening exposing a portion of the third metal structure. The capacitive biosensor further includes a sensing region on the interconnect structure. The sensing region includes a first sensing electrode and a second sensing electrode. The first sensing electrode is formed of the third conductive layer, and the second sensing electrode is disposed on the passivation layer.Type: GrantFiled: December 23, 2020Date of Patent: May 21, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Cheng-Ping Chang, Chien-Hui Li, Chien-Hsun Wu, Tai-I Yang, Yung-Hsiang Chen
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Patent number: 11973148Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.Type: GrantFiled: November 18, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
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Publication number: 20240117837Abstract: A foldable electronic device includes a first body, a second body, a first hinge module, a second hinge module, a driving sheet, and a one-way bearing. The first body has a display surface and a back surface. The first hinge module has a first shaft pivotally connected to the first body and a second shaft pivotally connected to the second body. The second shaft has a virtual axis. The second hinge module is disposed to the second body and has a rotating shaft. The rotating shaft is disposed corresponding to the virtual axis. The driving sheet is located between the first shaft and the second shaft, and is located between the first hinge module and the second hinge module. The one-way bearing is rotatably disposed around the rotating shaft. The one-way bearing has a bearing stop portion corresponding to the driving sheet.Type: ApplicationFiled: April 24, 2023Publication date: April 11, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Tsung-Ju Chiang, Yung-Hsiang Chen
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Patent number: 11901754Abstract: The disclosure provides a charging base. The charging base is applied to electrically connect to an electronic device and charge a stylus. The charging base includes: a base, a connector, a first charging end conductive structure, and a second charging end conductive structure. The base includes a through-hole. The connector is disposed on one side of the base and is used for being electrically connected to the electronic device. The first charging end conductive structure is formed on an upper surface of the base and is electrically connected to the connector. The second charging end conductive structure is formed in the through-hole and is electrically connected to the connector.Type: GrantFiled: January 27, 2022Date of Patent: February 13, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Chin Chung Lai, Yung-Hsiang Chen
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Publication number: 20240045343Abstract: A method includes providing a workpiece to a semiconductor apparatus, the workpiece including a material layer including a first strip having: a first plurality of exposure fields; and a second plurality of exposure fields alternatingly arranged with the first plurality of exposure fields. The method further includes: scanning the first strip along a first scan route from a first side of the workpiece to a second side of the workpiece to generate first topography measurement data; scanning the first strip along a second scan route from the second side to the first side to generate second topography measurement data; and exposing the first plurality of exposure fields and exposing the second plurality of exposure fields according to the first topography measurement data and the second topography measurement data.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Inventors: YUNG-YAO LEE, YEH-CHIN WANG, YANG-ANN CHU, YUNG-HSIANG CHEN, YUNG-CHENG CHEN