Patents by Inventor Yung-I Yeh
Yung-I Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200083132Abstract: A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.Type: ApplicationFiled: May 10, 2019Publication date: March 12, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yen-Chi HUANG, Hao-Chih HSIEH, Jin Han SHIH, Yung I. YEH, Tun-Ching PI
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Publication number: 20190348371Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.Type: ApplicationFiled: May 11, 2018Publication date: November 14, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG, Yung I. YEH
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Publication number: 20190109117Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.Type: ApplicationFiled: October 4, 2018Publication date: April 11, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh, Ming-Chiang Lee
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Patent number: 9984983Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.Type: GrantFiled: September 21, 2016Date of Patent: May 29, 2018Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Sheng Chung, Kuo-Hsien Liao, Jin-Feng Yang, Chen-Yin Tai, Yung-I Yeh
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Publication number: 20180122761Abstract: A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: Chun-Chin HUANG, Yung I. YEH, Che-Ming HSU
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Patent number: 9960137Abstract: A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor substrate; a first conductive pillar disposed on the first UBM layer; and a second conductive pillar disposed on the first conductive pillar. A material of the first conductive pillar is different from a material of the second conductive pillar, and the material of the second conductive pillar includes an antioxidant.Type: GrantFiled: November 1, 2016Date of Patent: May 1, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chun-Chin Huang, Yung I. Yeh, Che-Ming Hsu
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Publication number: 20170012007Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.Type: ApplicationFiled: September 21, 2016Publication date: January 12, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Sheng Chung, Kuo-Hsien Liao, Jin-Feng Yang, Chen-Yin Tai, Yung-I Yeh
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Patent number: 9484313Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.Type: GrantFiled: February 27, 2013Date of Patent: November 1, 2016Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Sheng Chung, Kuo-Hsien Liao, Jin-Feng Yang, Chen-Yin Tai, Yung-I Yeh
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Publication number: 20140239464Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Sheng Chung, Kuo-Hsien Liao, Jin-Feng Yang, Chen-Yin Tai, Yung-I Yeh
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Patent number: 8786060Abstract: A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point.Type: GrantFiled: May 4, 2012Date of Patent: July 22, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee Yen, Chi-Sheng Chung, Kuo-Hsien Liao, Yung-I Yeh
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Publication number: 20130292808Abstract: A semiconductor package includes a substrate, a semiconductor die, a package body, an electromagnetic interference shield, a dielectric structure and an antenna element. The substrate comprises a grounding segment and a feeding point. The semiconductor die is disposed on the substrate. The package body encapsulates the semiconductor die. The electromagnetic interference shield is formed on the package body. The dielectric structure encapsulates the electromagnetic interference shield. The antenna element is formed on the dielectric structure and electrically connecting the grounding segment of the substrate and the feeding point.Type: ApplicationFiled: May 4, 2012Publication date: November 7, 2013Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Han-Chee Yen, Chi-Sheng Chung, Kuo-Hsien Liao, Yung-I Yeh
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Patent number: 7375020Abstract: The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.Type: GrantFiled: November 19, 2004Date of Patent: May 20, 2008Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Hua Wu, Min-Lung Huang, Shih-Chang Lee, Jen-Kuang Fang, Yung-I Yeh
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Patent number: 7061084Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.Type: GrantFiled: September 5, 2003Date of Patent: June 13, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kun-Ching Chen, Yung I Yeh
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Patent number: 6960822Abstract: A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.Type: GrantFiled: August 7, 2003Date of Patent: November 1, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Chuan Ding, Yung-I Yeh
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Patent number: 6916732Abstract: A method of forming a plurality of bumps over a wafer. The wafer has an active surface having a passivation layer and a plurality of contact pads thereon. The passivation layer exposes the contact pads on the active surface. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the contact pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that expose the metallic layer. Flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is carried out so that the solder block bonds with the metallic layer. Finally, the flux material and the photoresist layer are removed.Type: GrantFiled: July 11, 2003Date of Patent: July 12, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Hua Wu, Min-Lung Huang, Shih-Chang Lee, Jen-Kuang Fang, Yung-I Yeh
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Publication number: 20050085061Abstract: The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.Type: ApplicationFiled: November 19, 2004Publication date: April 21, 2005Inventors: Tsung-Hua Wu, Min-Lung Huang, Shih-Chang Lee, Jen-Kuang Fang, Yung-I Yeh
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Publication number: 20040185651Abstract: A method of forming a plurality of bumps over a wafer. The wafer has an active surface having a passivation layer and a plurality of contact pads thereon. The passivation layer exposes the contact pads on the active surface. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the contact pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that expose the metallic layer. Flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is carried out so that the solder block bonds with the metallic layer. Finally, the flux material and the photoresist layer are removed.Type: ApplicationFiled: July 11, 2003Publication date: September 23, 2004Inventors: Tsung-Hua Wu, Min-Lung Huang, Shih-Chang Lee, Jen-Kuang Fang, Yung-I Yeh
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Patent number: 6795746Abstract: The internet bonding diagram system comprises a processing unit to process the information send by a user via a network. A blank lead frame/substrate database is coupled to the processing unit to store lead frame information. A job database is coupled to the processing unit to store information forwarded by a potential client, wherein the job database includes buyer satisfaction data provided by said user. A bonding diagram generator is coupled to the processing unit to generate a layout of bonding diagram in accordance with the information provided by the user. A forwarding module is responsive to the bonding diagram generator to forward the layout of bonding diagram to the user.Type: GrantFiled: March 22, 2001Date of Patent: September 21, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Min Chuang, I-Liang Lin, Chun-Kuang Lin, Yung-I Yeh
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Publication number: 20040150099Abstract: A cavity down multi-chips module package mainly comprises a substrate, a heat spreader, a plurality of chips and a carrier. The heat spreader is attached on the substrate via an adhesive so as to define a cavity through the opening passing through the substrate, and the carrier for redistributing electrical signals is disposed in the opening so as to be mounted on the heat spreader through another adhesive. Moreover, a plurality of chips are attached on the carrier and electrically connected to the carrier through first electrically conductive wires. Besides, the carrier is electrically connected to the substrate through second electrically conductive wires. Accordingly, the electrical signals can be transmitted from the chips to the substrate through the carrier, the first wires, and the second wires so as to shorten the electrical paths and to upgrade the electrical performance of the package.Type: ApplicationFiled: December 30, 2003Publication date: August 5, 2004Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Chuan Ding, Yung-I Yeh
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Publication number: 20040137659Abstract: A substrate includes a dielectric structure, an interconnection structure and a solder mask. The interconnection structure interlaces inside the dielectric structure. The solder mask covers the dielectric structure. The material of the solder mask can be the same as that of the dielectric structure contacting the solder mask. The material of the solder mask can be epoxy resin or bismaleimide-triazine.Type: ApplicationFiled: August 7, 2003Publication date: July 15, 2004Inventors: Yi-Chuan Ding, Yung-I Yeh