Abstract: An internet thermal data analysis system comprises a processing unit to process an information sent by a user via a network, wherein the information comprises a package information. A job database is coupled to the processing unit to store the package information sent by the user, a thermal analysis module is coupled to the processing unit to analysis the information sent by the user. A thermal data report generator is coupled to the processing unit to generate a thermal data simulation in accordance with the information sent by the user. A forwarding module is responsive to the thermal data report generator to forward the thermal data simulation to the user.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: An internet thermal data analysis system comprises a processing unit to process an information sent by a user via a network, wherein the information comprises a package information. A job database is coupled to the processing unit to store the package information sent by the user, a thermal analysis module is coupled to the processing unit to analysis the information sent by the user. A thermal data report generator is coupled to the processing unit to generate a thermal data simulation in accordance with the information sent by the user. A forwarding module is responsive to the thermal data report generator to forward the thermal data simulation to the user.

Abstract: A substrate strip includes a plurality of substrate units wherein each of the substrate units is accepted for packaging a semiconductor package. The substrate strip comprises: a frame having at least one opening; at least one first substrate unit integrally formed with the strip frame; and at least one second substrate unit disposed in the opening and securely attached to the strip frame by an adhesive. The present invention further provides a method for making the substrate strip. The method is conducted by separating defected substrate units from a substrate strip and securely attaching accepted substrate units back to the substrate strip.

Abstract: A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

Abstract: The internet bonding diagram system comprises a processing unit to process the information send by a user via a network. A blank lead frame/substrate database is coupled to the processing unit to store lead frame information. A job database is coupled to the processing unit to store information forwarded by a potential client, wherein the job database includes buyer satisfaction data provided by said user. A bonding diagram generator is coupled to the processing unit to generate a layout of bonding diagram in accordance with the information provided by the user. A forwarding module is responsive to the bonding diagram generator to forward the layout of bonding diagram to the user.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: A BGA semiconductor package comprises a chip mounted on the central region of the upper surface on the substrate. The substrate includes an upper surface, a lower surface, a ground plate disposed under the upper surface, and at least one power plate disposed between the ground plate and the lower surface. A ground ring surrounds the periphery of the chip and possesses a first set of serrated portions extending toward the outer edge of the substrate. A first power ring surrounds the ground ring and possesses a second set of serrated portions extending among the first set of serrated portions of the ground ring, such that the extending portions of the first and second sets of serrated rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip surface to the extending portions of the first and the second serrated rings are comparable.

Abstract: A BGA semiconductor package structure that is able to avoid high frequency interference has at least one non-ball mounting area on a bottom face of a substrate, wherein high frequency bump balls are mounted abreast on the non-ball mounting ball area. When the BGA package device is mounted on a PCB, the non-ball mounting area correspond the electric wires, such that the electric wires which are formed on the PCB are able to transmit high frequency signals and connect the high frequency bump balls. Thus, when the high frequency signals are transmitted via the electric wires, the high frequency signals do not affect other signals transmitted via other electric wires.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: In a flip chip process, a wafer is provided with a plurality of chips therein. Each chip has an active surface on which are formed a plurality of bonding pads. A bump is formed on each bonding pad. A plurality of substrates respectively includes at least a package unit, wherein each package unit has a plurality of contact pads. The substrates are respectively mounted onto the wafer such that each package unit corresponds to one chip and the contact pads of the package unit are respectively connected to the corresponding bumps, wherein two neighboring substrates are separated by a gap. An underfill material fills between the wafer and the substrates, the underfill material being introduced through the gaps between the substrates and from the boundary of the wafer. The underfill material then is solidified. The substrates and the wafer are diced to form individualized packages.

Abstract: A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

Abstract: A flexible substrate includes a substrate constructed in a form of a tape, the substrate including patterns formed on at least one of an upper side and a bottom side thereof. The tape includes sprocket holes defied in each of two lateral edges thereof. A supporting layer is applied to at least one of the upper side and the bottom side of the substrate at an area not covered by the patterns to reinforce the substrate.

Abstract: The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces.

Abstract: A BGA package includes a chip with an array pad design disposed on the upper surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof, and the bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. Only power supply pads and ground pads are designed to be located in the outer row of bonding pads, and all of the I/O pads are designed to be located in the middle row of the bonding pads and the inner row of the bonding pads.

Abstract: A packaged semi-conductor substrate includes a package encapsulant pouring area, a layout provided on the substrate, a layer of solder mask deposited on the layout, and a film provided on the solder mask. When the package encapsulant is pouted into the package encapsulant pouring area, the package encapsulant is isolated from the solder mask by the film. An adhering force between the film and the package encapsulant is greater than an adhering force between the film and the mask such that the film is degated along with the package encapsulant in the pouring channel during a degating procedure of the pouring channel after a pouring procedure of the package encapsulant. Thus, the film and the package encapsulant are not residual on the substrate.

Abstract: A semiconductor packaging device includes a printed circuit board substrate, a mold gate formed on a periphery of the printed circuit board substrate through which a package encapsulant is poured to enclose electric elements mounted on a side of the printed circuit board, and a layer of non-metallic material covered on the side of the printed circuit board substrate in the mold gate area. The package encapsulant, after hardened, is bonded with the layer of non-metallic material, and the bonded package encapsulant/the layer of non-metallic material is degatable from the mold gate.