Patents by Inventor Yurii Vlasov

Yurii Vlasov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230289585
    Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Inventors: Tayfun Gokmen, Seyoung Kim, Dennis M. Newns, Yurii A. Vlasov
  • Patent number: 11741352
    Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 29, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Seyoung Kim, Dennis M. Newns, Yurii A. Vlasov
  • Publication number: 20230111302
    Abstract: Provided are electrochemical sensors for analyzing analytes. The sensors may comprise an implantable probe for analyzing a biological analyte, with those sensors described as electrochemical biosensors. Also provided are related methods of using and making the sensors. The electrochemical sensor is formed with an integrated on-chip probe body that provides for a buried microelectrode in a microfluidic channel etched in the probe body, such as a doped Si substrate. The fluidic system can, therefore, be quite small and suitable for in-vivo implantation and use, while withstanding high pressure. The fluidic system has specially-configured reagent channel to provide for periodic and convenient calibration, electrode cleaning and/or regeneration, without having to remove any sensor component from the implantation site.
    Type: Application
    Filed: September 23, 2022
    Publication date: April 13, 2023
    Inventors: Yurii VLASOV, Christopher Kenji BRENDEN
  • Patent number: 11263521
    Abstract: A device, system, product and method of controlling resistive processing units (RPUs), includes applying an input voltage signal to each node of an array of resistive processing units, and controlling a learning rate of the array of resistive processing units by varying an amplitude of the input voltage signal to the array of resistive processing units. A conductance state of the array of resistive processing units is varied according to the amplitude received at each of the resistive processing units of the array of resistive processing units. The controlling of the amplitude of input voltage signal is according to a processor of a control device.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Yurii A. Vlasov
  • Publication number: 20210393175
    Abstract: Provided are implantable probes for analyzing biological fluids and related methods of using and making. The probe is formed with an integrated on-chip probe body that provides for collection and storage of analyte from biological fluid and facilitates subsequent analysis, including by a mass spectrometer (MS). The analysis has high spatial accuracy as the probe tip that collects biological fluid sample is small, including less than 100 ?m with an opening less than 10 ?m. Temporal information can be obtained by storing the analyte from the biological fluid as a train of droplets separated by an immiscible fluid. The probe body can be electrically energized to facilitate sample ionization and transfer to a MS analysis device. In this manner, the integrated on-chip probe body facilitates analyte collection, storage and subsequent analysis within a single probe body material, including a doped silicon material.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 23, 2021
    Inventors: Yurii VLASOV, Yan ZHANG, Christopher Kenji BRENDEN, Prasoon Kumar JHA, Yifei YAN, Sungho KIM
  • Patent number: 10839292
    Abstract: A neural network system comprises a plurality of neurons, comprising a layer of input neurons, one or more layers of hidden neurons, and a layer of output neurons. The system further comprises a plurality of arrays of weights, each array of weights being configured to receive a plurality of discrete data points from a first layer of neurons and to produce a corresponding discrete data point to a second layer of neurons during a feed forward operation, each array of weights comprising a plurality of resistive processing units (RPU) having respective settable resistances. The system includes a neuron control system configured to control an operation mode of each of the plurality of neurons, wherein the operation mode comprises: a feed forward mode, a back propagation mode, and a weight update mode.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Yurii A. Vlasov
  • Patent number: 10664745
    Abstract: An array of resistive processing units (RPUs) comprises a plurality of rows of RPUs and a plurality of columns of RPUs wherein each RPU comprises an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column. A first storage is configured to store a weight value of the RPU, and a second storage is configured to store an amount of change to the weight value of the RPU. When the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the RPU is added to the weight value of the RPU.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Michael P. Perrone, Yurii A. Vlasov
  • Patent number: 10373051
    Abstract: Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Seyoung Kim, Yurii A. Vlasov
  • Patent number: 10248907
    Abstract: Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tayfun Gokmen, Seyoung Kim, Yurii Vlasov
  • Publication number: 20180060726
    Abstract: A device, system, product and method of controlling resistive processing units (RPUs), includes applying an input voltage signal to each node of an array of resistive processing units, and controlling a learning rate of the array of resistive processing units by varying an amplitude of the input voltage signal to the array of resistive processing units. A conductance state of the array of resistive processing units is varied according to the amplitude received at each of the resistive processing units of the array of resistive processing units. The controlling of the amplitude of input voltage signal is according to a processor of a control device.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Tayfun Gokmen, Yurii A. Vlasov
  • Publication number: 20180053089
    Abstract: A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: Tayfun Gokmen, Seyoung Kim, Dennis M. Newns, Yurii A. Vlasov
  • Publication number: 20180005110
    Abstract: An array of resistive processing units (RPUs) comprises a plurality of rows of RPUs and a plurality of columns of RPUs wherein each RPU comprises an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column. A first storage is configured to store a weight value of the RPU, and a second storage is configured to store an amount of change to the weight value of the RPU. When the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the RPU is added to the weight value of the RPU.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Tayfun Gokmen, Michael P. Perrone, Yurii A. Vlasov
  • Publication number: 20180005115
    Abstract: A neural network system comprises a plurality of neurons, comprising a layer of input neurons, one or more layers of hidden neurons, and a layer of output neurons. The system further comprises a plurality of arrays of weights, each array of weights being configured to receive a plurality of discrete data points from a first layer of neurons and to produce a corresponding discrete data point to a second layer of neurons during a feed forward operation, each array of weights comprising a plurality of resistive processing units (RPU) having respective settable resistances. The system includes a neuron control system configured to control an operation mode of each of the plurality of neurons, wherein the operation mode comprises: a feed forward mode, a back propagation mode, and a weight update mode.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Tayfun Gokmen, Yurii A. Vlasov
  • Publication number: 20170109628
    Abstract: Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Tayfun Gokmen, Seyoung Kim, Yurii A. Vlasov
  • Publication number: 20170109626
    Abstract: Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 20, 2017
    Inventors: Tayfun Gokmen, Seyoung Kim, Yurii A. Vlasov
  • Patent number: 9547125
    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Solomon Assefa, William M. Green, Steven M. Shank, Yurii A. Vlasov
  • Patent number: 9455372
    Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yurii A. Vlasov, Fengnian Xia
  • Patent number: 9243784
    Abstract: A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Paul F. Fortier, Stephane G. Harel, Yurii A. Vlasov
  • Patent number: 9236287
    Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDIES INC.
    Inventors: Solomon Assefa, William M. Green, Marwan H. Khater, Yurii A. Vlasov
  • Patent number: 9229164
    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolates the first and second silicon-on-insulator region. Within the STI region, a germanium material is deposited adjacent an end facet of the semiconductor optical waveguide. The germanium material forms an active region that receives propagating optical signals from the end facet of the semiconductor optical waveguide.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Solomon Assefa, William M. Green, Steven M. Shank, Yurii A. Vlasov