Abstract: A polarization splitter and rotator of a wafer chip, an opto-electronic device and method of use is disclosed. The first waveguide of the wafer chip is configured to receive an optical signal from an optical device and propagate a transverse electric eigenstate of the received optical signal. The second waveguide is configured to receive a transverse magnetic eigenstate of the received optical signal from the first waveguide. The second waveguide includes a splitter end, a middle section and a rotator end, wherein the splitter end includes a layer of polycrystalline silicon, a layer of silicon oxide and a layer of silicon nitride, the rotated end includes a layer single crystal silicon, a layer silicon oxide and a layer of silicon nitride, and the middle section includes layers of single crystal silicon, silicon oxide polycrystalline silicon and silicon nitride.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Abstract: A technique is provided for configuring an optical receiver. A photo detector is connected to a load resistor, and the photo detector includes an internal capacitance. A current source is connected through a switching circuit to the load resistor and to the photo detector. The current source is configured to discharge the internal capacitance of the photo detector. The switching circuit is configured to connect the current source to the internal capacitance based on a previous data bit.

Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.

Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide.

Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.

Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate.

Abstract: Line trenches are formed in a stack of a bulk semiconductor substrate and an oxygen-impermeable layer such that the depth of the trenches in the bulk semiconductor substrate is greater than the lateral spacing between a pair of adjacently located line trenches. Oxygen-impermeable spacers are formed on sidewalls of the line trenches. An isotropic etch, either alone or in combination with oxidation, removes a semiconductor material from below the oxygen-impermeable spacers to expand the lateral extent of expanded-bottom portions of the line trenches, and to reduce the lateral spacing between adjacent expanded-bottom portions. The semiconductor material around the bottom portions is oxidized to form a semiconductor oxide portion that underlies multiple oxygen-impermeable spacers. Semiconductor-on-insulator (SOI) portions are formed above the semiconductor oxide portion and within the bulk semiconductor substrate.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Abstract: A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion.

Abstract: A method for assembling a semiconductor photonic package device includes bonding a portion of a first surface of a semiconductor die portion to a portion of a carrier portion, bonding a single mode optical ferrule portion to a portion of the first surface of the semiconductor die portion, and disposing a cover plate assembly in contact with the optical ferrule portion and the carrier portion.

Abstract: A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer.

Abstract: A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer.

Abstract: A mode-selective add/drop unit for a mode division de/multiplexing device includes an optical ADU waveguide adapted for coupling to an input optical waveguide. The optical ADU waveguide includes at least one region providing optical signal coupling between the ADU waveguide and a multi-mode waveguide; and, one or more phase matching regions for controlling a relative or absolute phase difference between an electromagnetic wave (EMW) carried in the ADU waveguide and the multi-mode waveguide. The mode-selective add/drop unit may further include a transition region connecting the coupling region and a phase matching region, wherein a shape of a transition region is governed by a polynomial function, exponential function, logarithmic function, trigonometric function or, any combination of these functions.

Abstract: Photonic SOI devices are formed by lateral epitaxy of a deposited non-crystalline semiconductor layer over a localized buried oxide created by a trench isolation process or by thermal oxidation. Specifically, and after forming a trench into a semiconductor substrate, the trench can be filled with an oxide by a deposition process or a thermal oxidation can be performed to form a localized buried oxide within the semiconductor substrate. In some embodiments, the oxide can be recessed to expose sidewall surfaces of the semiconductor substrate. Next, a non-crystalline semiconductor layer is formed and then a solid state crystallization is preformed which forms a localized semiconductor-on-insulator layer. During the solid state crystallization process portions of the non-crystalline semiconductor layer that are adjacent exposed sidewall surfaces of the substrate are crystallized.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide. One or more process steps may be performed simultaneously on the CMOS devices and the photonics devices.

Abstract: Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector.

Abstract: A semiconductor structure includes a photonic modulator and a field effect transistor on a same substrate. The photonic modulator includes a modulator semiconductor structure and a semiconductor contact structure employing a same semiconductor material as a gate electrode of a field effect transistor. The modulator semiconductor structure includes a lateral p-n junction, and the semiconductor contact structure includes another lateral p-n junction. To form this semiconductor structure, the modulator semiconductor structure in the shape of a waveguide and an active region of a field effect transistor region can be patterned in a semiconductor substrate. A gate dielectric layer is formed on the modulator semiconductor structure and the active region, and is subsequently removed from the modulator semiconductor structure.