Patents by Inventor Yusuke Kato

Yusuke Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294148
    Abstract: An antenna includes a first conductor plate and a second conductor plate, the second conductor plate being disposed in the first conductor plate so as to be apart from the first conductor plate with a distance between both plates; wherein the first conductor plate includes a first U-shaped portion, the first U-shaped portion being formed in a U-shape so as to include a first side portion, a second side portion opposed to the first side portion, and a first front portion connected between the first side portion and the second side portion; wherein the second conductor plate includes a second U-shaped portion, the second U-shaped portion being formed in a U-shape so as to include a third side portion, a fourth side portion opposed to the third side portion, and a second front portion connected between the third side portion and the fourth side portion.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 6, 2025
    Assignee: AGC INC.
    Inventors: Toshiki Sayama, Hideaki Shoji, Yusuke Kato, Shoichi Takeuchi
  • Patent number: 12294137
    Abstract: An antenna system for vehicles includes a first antenna attached in a vicinity of a windshield of a vehicle; and a second antenna attached in a vicinity of a rear glass of the vehicle, wherein the first antenna and the second antenna are configured to transmit and receive an electromagnetic wave in a predetermined frequency band F, and wherein defining a region A and a region B with respect to a vehicle center axis extending in a traveling direction of the vehicle, so as to bisect a vehicle width of the vehicle from a viewpoint in a direction normal to a horizontal plane, the first antenna is arranged in the region A, and the second antenna is arranged in the region B.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: May 6, 2025
    Assignee: AGC INC.
    Inventors: Toshiki Sayama, Hideaki Shoji, Yusuke Kato, Shoichi Takeuchi
  • Patent number: 12294707
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: May 6, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Yusuke Kato, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 12294696
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: May 6, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Jing Ya Li, Chong Soon Lim, Han Boon Teo, Che Wei Kuo, Hai Wei Sun, Chu Tong Wang, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Publication number: 20250141103
    Abstract: An antenna including: a radiating plate having a radiating surface; a ground plate disposed on the radiating plate with a dielectric interposed therebetween; and a parasitic element including: a first parasitic conductor disposed in a first direction with respect to a center of gravity of the radiating plate in a plan view of the radiating plate; a second parasitic conductor disposed in a second direction opposite to the first direction with respect to the center of gravity of the radiating plate in a plan view of the radiating plate; and a third parasitic conductor connecting the first parasitic conductor and the second parasitic conductor, in which the third parasitic conductor includes a portion that passes in a vicinity of the center of gravity of the radiating plate and extends in the first direction and the second direction in a plan view of the radiating plate.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 1, 2025
    Applicant: AGC Inc.
    Inventors: Toshiki SAYAMA, Hideaki Shoji, Yusuke Kato, Shoichi Takeuchi
  • Publication number: 20250142098
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry determines one or more tiles included in a picture and one or more subpictures included in the picture, according to a constraint condition that each tile of the one or more tiles includes at least one subpicture of the one or more subpictures entirely and the each tile does not include another subpicture of the one or more subpictures partially.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Inventors: Kiyofumi ABE, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Patent number: 12289462
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry writes, into a bitstream, a first flag indicating whether or not to enable a first process of applying a filter to a first image to generate a second image, holding the second image as a reference image, and displaying the second image. When the first process is not enabled, circuitry writes, into the bitstream, one or more parameters for controlling a second process of applying the filter to the first image to generate the second image, holding the first image as a reference image, and displaying the second image.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 29, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Han Boon Teo, Hai Wei Sun, Jing Ya Li, Che Wei Kuo, Chong Soon Lim, Chu Tong Wang, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Patent number: 12284376
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes, per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: April 22, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Virginie Drugeon, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Patent number: 12267499
    Abstract: A decoder includes circuitry and memory. In both of a first type of residual decoding where an inverse orthogonal transform is applied and a second type of residual decoding where the inverse orthogonal transform is skipped, wherein when a restriction on a number of CABAC processes allows CABAC decoding of a set of coefficient information flags, the circuitry: decodes the coefficient information flags by CABAC; and otherwise, the circuitry: skips the CABAC decoding of the coefficient information flags; and the circuitry decodes a remainder value of the coefficient with Golomb-Rice decoding when the coefficient information flags are decoded; and otherwise the circuitry decodes a value of the coefficient with the Golomb-Rice decoding, wherein in the second type of residual decoding, the circuitry decodes absolute value flags each relating to an absolute value of the coefficient after decoding the coefficient information flags and before decoding the remainder value of the coefficient.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 1, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yusuke Kato, Takahiro Nishi, Tadamasa Toma, Kiyofumi Abe
  • Publication number: 20250106440
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Han Boon TEO, Jing Ya LI, Che-Wei KUO, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Patent number: 12262004
    Abstract: An encoder includes circuitry which generates a first coefficient value by applying a CCALF process to a first reconstructed image sample of a luma component; generates a second coefficient value by applying an ALF process to a second reconstructed image sample of a chroma component; generates a third coefficient value by adding the first coefficient value to the second coefficient value; and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry writes a first parameter into a sequence parameter set; writes a second parameter into a parameter set of a picture in response to a value of the first parameter being 1; writes a third parameter into a slice header in response to the value of the first parameter being 1; and writes a fourth parameter into a coding tree unit in response to a value of the third parameter being 1.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Che-Wei Kuo, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Patent number: 12262058
    Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: March 25, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Masato Ohkawa, Hideo Saitou, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Patent number: 12262038
    Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.
    Type: Grant
    Filed: January 22, 2024
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Che-Wei Kuo, Chong Soon Lim, Han Boon Teo, Jing Ya Li, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Publication number: 20250097476
    Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from ?27 to 27?1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 20, 2025
    Inventors: Jing Ya LI, Han Boon TEO, Chong Soon LIM, Hai Wei SUN, Che-Wei KUO, Chu Tong WANG, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250097456
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: derives a motion vector of a current block by referring to at least one reference picture different from a picture to which the current block belongs; performs a mode for estimating, for each sub-block unit of sub-blocks obtained by splitting the current block, a surrounding region of the motion vector to correct the motion vector; determines whether to apply deblocking filtering to each of boundaries between neighboring ones of the sub-blocks; and applies the deblocking filtering to the boundary, based on a result of the determination.
    Type: Application
    Filed: November 29, 2024
    Publication date: March 20, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250097477
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, and generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry modifies the first coefficient value by performing an arithmetic right shift by 7 bits on the first coefficient value. The circuitry generates a third coefficient value by adding the modified first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Jing Ya LI, Chong Soon LIM, Han Boon TEO, Hai Wei SUN, Che-Wei KUO, Chu Tong WANG, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250083458
    Abstract: A liquid ejecting device includes a device main body including a liquid ejecting head, a reading unit configured to be opened and closed at a top of the device main body and read an image of a document, and a liquid accommodating unit disposed at a device front surface that is a side surface directly opposite to a user among side surfaces of the device main body, the liquid accommodating unit being configured to accommodate the liquid to be ejected from the liquid ejecting head, wherein the reading unit includes a notch portion at a corner portion on a device front side, and a part of the liquid accommodating unit is inserted into the notch portion, and a space above the liquid accommodating unit is open.
    Type: Application
    Filed: September 5, 2024
    Publication date: March 13, 2025
    Inventors: Hisayuki AKAHANE, Jun YODA, Keisuke SASAKI, Yusuke KATO
  • Publication number: 20250083447
    Abstract: A liquid ejecting device includes a device main body including a liquid ejecting head configured to eject a liquid to a medium and a liquid accommodating unit configured to accommodate the liquid to be ejected from the liquid ejecting head, wherein the liquid accommodating unit includes a supplying port of the liquid and an opening and closing cover configured to be switched between a closed state in which the supplying port is covered and an open state in which the supplying port is exposed, and a light-emitting unit is provided at the opening and closing cover, the light-emitting unit being configured to emit light in accordance with a remaining amount of the liquid accommodated in the liquid accommodating unit.
    Type: Application
    Filed: September 5, 2024
    Publication date: March 13, 2025
    Inventors: Yusuke KATO, Rina TODA
  • Patent number: 12244809
    Abstract: An encoder including circuitry and memory coupled to the circuitry. In both of a first case where an orthogonal transform is performed and a second case where the orthogonal transform is skipped, when a number of CABAC processes is within an allowable range, the circuitry: encodes a plurality of coefficient information flags by CABAC; and encodes a remainder value of the coefficient; and when the number of CABAC processes is not within the allowable range, the circuitry: skips the encoding of the plurality of coefficient information flags, wherein in the first case, the circuitry: converts the coefficient to a second coefficient by using a poszero value that is determined using a plurality of surrounding coefficients; and encodes a value of the second coefficient, and wherein in the second case, the circuitry: encodes the value of the coefficient.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 4, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yusuke Kato, Takahiro Nishi, Tadamasa Toma, Kiyofumi Abe
  • Publication number: 20250071279
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: performs quantization on a plurality of transform coefficients of a current block to be encoded, using a quantization matrix when orthogonal transform is performed on the current block and secondary transform is not performed on the current block; and performs quantization on the plurality of transform coefficients of the current block without using the quantization matrix when orthogonal transform is not performed on the current block and when both orthogonal transform and secondary transform are performed on the current block.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO