Patents by Inventor Yusuke Nonaka

Yusuke Nonaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411788
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 31, 2020
    Inventors: Satoshi SEO, Takahiro ISHISONE, Nobuharu OHSAWA, Yusuke NONAKA, Toshiki SASAKI
  • Patent number: 10788996
    Abstract: The present invention effectively utilizes computation resources by allocating the computation resources, in accordance with conditions, to a process that shares a computation resource with another process and a process that occupies a computation resource. Execution control causes a processor core allocated to a storage control process to be occupied by the storage control process, the execution control causes a processor core allocated to an application process to be shared with another process, and the execution control changes the number of processor cores allocated to the storage control process on the basis of I/O information indicating a state of an I/O.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 29, 2020
    Assignee: HITACHI, LTD.
    Inventors: Masakuni Agetsuma, Hiroaki Akutsu, Yusuke Nonaka
  • Publication number: 20200280013
    Abstract: Provided is a light-emitting element which includes a first electrode, a second electrode over the first electrode, and first and second light-emitting layers therebetween. The first light-emitting layer contains a first host material and a first light-emitting material, and the second light-emitting layer contains a second host material and a second light-emitting material. The first light-emitting material is a fluorescent material, and the second light-emitting material is a phosphorescent material. The level of the lowest triplet excited state (T1 level) of the first light-emitting material is higher than the T1 level of the first host material. A light-emitting device, an electronic device, and a lighting device including the light-emitting element are further provided.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 3, 2020
    Inventors: Takahiro ISHISONE, Satoshi SEO, Yusuke NONAKA, Nobuharu OHSAWA
  • Publication number: 20200266289
    Abstract: A semiconductor device with favorable electrical characteristics and reliability is provided. A first insulator is formed. A second insulator is formed over the first insulator. An island-shaped oxide is formed over the second insulator. A stacked body of a third insulator and a conductor is formed over the oxide. The resistance of the oxide is selectively reduced by forming a film containing a metal element over the oxide and the stacked body. After a fourth insulator is formed over the second insulator, the oxide, and the stacked body, an opening portion exposing the second insulator is formed in the fourth insulator. A fifth insulator is formed over the second insulator and the fourth insulator. Oxygen introduction treatment is performed on the fifth insulator.
    Type: Application
    Filed: August 28, 2018
    Publication date: August 20, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Naoki OKUNO, Noritaka ISHIHARA, Yusuke NONAKA
  • Publication number: 20200266281
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first insulator; a first oxide provided over the first insulator; a second oxide provided over the first oxide; a first conductor and a second conductor provided apart from each other over the second oxide; a third oxide provided over the second oxide, the first conductor, and the second conductor; a second insulating film provided over the third oxide; and a third conductor provided over the second oxide with the third oxide and the second insulating film positioned therebetween. The third oxide contains a metal element and nitrogen, and the metal element is bonded to nitrogen.
    Type: Application
    Filed: October 29, 2018
    Publication date: August 20, 2020
    Inventors: Shunpei YAMAZAKI, Tomoki HIRAMATSU, Yusuke NONAKA, Noritaka ISHIHARA, Shota SAMBONSUGE, Yasumasa YAMANE, Yuta ENDO
  • Patent number: 10741679
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Publication number: 20200212223
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Publication number: 20200194310
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Application
    Filed: August 28, 2018
    Publication date: June 18, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
  • Patent number: 10686152
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone, Nobuharu Ohsawa, Yusuke Nonaka, Toshiki Sasaki
  • Patent number: 10686153
    Abstract: Provided is a light-emitting element which includes a first electrode, a second electrode over the first electrode, and first and second light-emitting layers therebetween. The first light-emitting layer contains a first host material and a first light-emitting material, and the second light-emitting layer contains a second host material and a second light-emitting material. The first light-emitting material is a fluorescent material, and the second light-emitting material is a phosphorescent material. The level of the lowest triplet excited state (T1 level) of the first light-emitting material is higher than the T1 level of the first host material. A light-emitting device, an electronic device, and a lighting device including the light-emitting element are further provided.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Ishisone, Satoshi Seo, Yusuke Nonaka, Nobuharu Ohsawa
  • Publication number: 20200185523
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
  • Patent number: 10628083
    Abstract: A storage controller measures a RAID group (RG) operating time, which is the operating time of an RG. The storage controller then corrects the measured RG operating time, which is used to calculate the operating rate of the RG, on the basis of a correction coefficient associated with the type of the physical devices (PDEVs) constituting the RG, and on the basis of the RG backend multiplicity, which is the multiplicity of the I/O commands transmitted to the RG.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 21, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takao Yoshikawa, Yusuke Nonaka, Jin Choi, Masahide Kawarasaki
  • Patent number: 10622485
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: April 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 10615079
    Abstract: A buried n-type region is provided in a surface layer portion of an n-type body layer of a Pch MOSFET. This makes it possible to lower the threshold voltage Vt. In a portion of the n-type body layer other than the buried n-type region, since an n-type impurity concentration can be kept relatively high, the threshold voltage Vt can be lowered while securing an on-breakdown voltage. Furthermore, since an accumulation region is configured by an n-type active layer, a partial high concentration portion is not formed in a p-type drift layer. Therefore, as in the case where the partial high concentration portion is generated in the p-type drift layer, a reduction in a breakdown voltage caused by an electric field concentration can be restricted from occurring with a distribution in which equipotential lines are concentrated.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 7, 2020
    Assignee: DENSO CORPORATION
    Inventors: Shogo Ikeura, Yusuke Nonaka, Shinichirou Yanagi, Seiji Noma, Shinya Sakurai
  • Patent number: 10586869
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 10579275
    Abstract: This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 3, 2020
    Assignee: HITACHI, LTD.
    Inventors: Akihiko Araki, Yusuke Nonaka, Noboru Morishita
  • Publication number: 20190385327
    Abstract: An image processing method is performed by a computer for estimating a width of a crack or the like. The method includes: extracting a linear region in which a linear damage appears from an image of an object captured by an imaging apparatus; calculating a luminance information sum by adding luminance information of each pixel included in the linear region in a direction crossing the linear region; and estimating, from the calculated luminance information sum, based on a relational expression indicating a relationship between luminance information sum and a width of a damage, a width of the linear damage.
    Type: Application
    Filed: April 30, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: YUSUKE NONAKA, EIGO SEGAWA
  • Patent number: 10468619
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone, Nobuharu Ohsawa, Yusuke Nonaka, Toshiki Sasaki
  • Patent number: 10468536
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 10449789
    Abstract: A printer includes a first holding shaft holding side pinch rollers and at least one center pinch roller, grit rollers moving a recording medium while holding the recording medium together with the side pinch rollers and together with the center pinch roller, and a rotator rotating the first holding shaft to cause the side pinch rollers and the center pinch roller to approach, or to be separated from, the grit rollers. The center pinch roller is movable in a direction to be separated from the recording medium, independently from the side pinch rollers.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 22, 2019
    Assignee: ROLAND DG CORPORATION
    Inventors: Ryosuke Nonaka, Yusuke Takano