Patents by Inventor Yusuke Nonaka

Yusuke Nonaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10615079
    Abstract: A buried n-type region is provided in a surface layer portion of an n-type body layer of a Pch MOSFET. This makes it possible to lower the threshold voltage Vt. In a portion of the n-type body layer other than the buried n-type region, since an n-type impurity concentration can be kept relatively high, the threshold voltage Vt can be lowered while securing an on-breakdown voltage. Furthermore, since an accumulation region is configured by an n-type active layer, a partial high concentration portion is not formed in a p-type drift layer. Therefore, as in the case where the partial high concentration portion is generated in the p-type drift layer, a reduction in a breakdown voltage caused by an electric field concentration can be restricted from occurring with a distribution in which equipotential lines are concentrated.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 7, 2020
    Assignee: DENSO CORPORATION
    Inventors: Shogo Ikeura, Yusuke Nonaka, Shinichirou Yanagi, Seiji Noma, Shinya Sakurai
  • Patent number: 10586869
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 10579275
    Abstract: This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 3, 2020
    Assignee: HITACHI, LTD.
    Inventors: Akihiko Araki, Yusuke Nonaka, Noboru Morishita
  • Publication number: 20190385327
    Abstract: An image processing method is performed by a computer for estimating a width of a crack or the like. The method includes: extracting a linear region in which a linear damage appears from an image of an object captured by an imaging apparatus; calculating a luminance information sum by adding luminance information of each pixel included in the linear region in a direction crossing the linear region; and estimating, from the calculated luminance information sum, based on a relational expression indicating a relationship between luminance information sum and a width of a damage, a width of the linear damage.
    Type: Application
    Filed: April 30, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: YUSUKE NONAKA, EIGO SEGAWA
  • Patent number: 10468536
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Patent number: 10468619
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone, Nobuharu Ohsawa, Yusuke Nonaka, Toshiki Sasaki
  • Publication number: 20190319211
    Abstract: An object of one embodiment of the present invention is to provide a multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance, a separation layer containing a substance having a hole-transport property and a substance having an electron-transport property, and a second light-emitting layer containing two kinds of organic compounds that form an exciplex and a substance that can convert triplet excitation energy into luminescence. Note that a light-emitting element in which light emitted from the first light-emitting layer has an emission spectrum peak on the shorter wavelength side than an emission spectrum peak of the second light-emitting layer is more effective.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Nobuharu OHSAWA, Yusuke NONAKA, Takahiro ISHISONE, Satoshi SEO, Takuya KAWATA
  • Patent number: 10439005
    Abstract: A multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application is provided. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance and a second light-emitting layer containing two kinds of organic compounds and a substance that can convert triplet excitation energy into luminescence. Note that light emitted from the first light-emitting layer has an emission peak on the shorter wavelength side than light emitted from the second light-emitting layer.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Ishisone, Satoshi Seo, Yusuke Nonaka, Nobuharu Ohsawa
  • Patent number: 10439158
    Abstract: A light-emitting element includes a stack of a first light-emitting layer emitting fluorescent light and a second light-emitting layer emitting phosphorescent light between a pair of electrodes. The second light-emitting layer includes a first layer in which an exciplex is formed, a second layer in which an exciplex is formed, and a third layer in which an exciplex is formed. The second layer is located over the first layer, and the third layer is located over the second layer. An emission peak wavelength of the second layer is longer than an emission peak wavelength of the first layer and an emission peak wavelength of the third layer.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Kawata, Nobuharu Ohsawa, Yusuke Nonaka, Takahiro Ishisone, Satoshi Seo
  • Publication number: 20190279906
    Abstract: A buried n-type region is provided in a surface layer portion of an n-type body layer of a Pch MOSFET. This makes it possible to lower the threshold voltage Vt. In a portion of the n-type body layer other than the buried n-type region, since an n-type impurity concentration can be kept relatively high, the threshold voltage Vt can be lowered while securing an on-breakdown voltage. Furthermore, since an accumulation region is configured by an n-type active layer, a partial high concentration portion is not formed in a p-type drift layer. Therefore, as in the case where the partial high concentration portion is generated in the p-type drift layer, a reduction in a breakdown voltage caused by an electric field concentration can be restricted from occurring with a distribution in which equipotential lines are concentrated.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 12, 2019
    Inventors: Shogo IKEURA, Yusuke NONAKA, Shinichirou YANAGI, Seiji NOMA, Shinya SAKURAI
  • Patent number: 10410054
    Abstract: An image processing method causing an image processing device to execute a process including: obtaining a first image and a second image captured at different timings for an identical inspection target by passing through an imaging range of an image sensor row; extracting respective feature points of the first image and the second image; associating the feature points of the first image and the feature points of the second image with each other; estimating a conversion formula to convert the feature point of the second image to the feature point of the first image based on a restraint condition of a quadratic equation, in accordance with respective coordinates of three or more sets of the feature points associated between the first image and the second image; and converting the second image into a third image corresponding to the first image based on the estimated conversion formula.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 10, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yusuke Nonaka, Eigo Segawa
  • Patent number: 10374186
    Abstract: An object of one embodiment of the present invention is to provide a multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance, a separation layer containing a substance having a hole-transport property and a substance having an electron-transport property, and a second light-emitting layer containing two kinds of organic compounds that form an exciplex and a substance that can convert triplet excitation energy into luminescence. Note that a light-emitting element in which light emitted from the first light-emitting layer has an emission spectrum peak on the shorter wavelength side than an emission spectrum peak of the second light-emitting layer is more effective.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Nobuharu Ohsawa, Yusuke Nonaka, Takahiro Ishisone, Satoshi Seo, Takuya Kawata
  • Publication number: 20190237585
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: April 11, 2019
    Publication date: August 1, 2019
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Publication number: 20190229219
    Abstract: A semiconductor device includes: a semiconductor substrate having a diode formation region; an upper diffusion region of a first conductivity type provided on a surface layer of a main surface of the semiconductor substrate in the diode formation region; and a lower diffusion region of a second conductivity type provided at a position deeper than the upper diffusion region with respect to the main surface in a depth direction of the semiconductor substrate, the lower diffusion region having a higher impurity concentration as compared to the semiconductor substrate. The lower diffusion region provides a PN joint surface with the upper diffusion region at a position deeper than the main surface, and has a maximum point indicating a maximum concentration in an impurity concentration profile of the lower diffusion region in the diode formation region.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 25, 2019
    Inventors: Shinichirou YANAGI, Yusuke NONAKA, Seiji NOMA, Shinya SAKURAI, Shogo IKEURA, Atsushi KASAHARA, Shin TAKIZAWA
  • Patent number: 10353613
    Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: July 16, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Akihiko Araki, Yusuke Nonaka, Masanori Takada, Naoya Okada
  • Patent number: 10290744
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Masashi Tsubuku, Yusuke Nonaka, Takashi Shimazu, Shunpei Yamazaki
  • Publication number: 20190140027
    Abstract: A multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application is provided. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance and a second light-emitting layer containing two kinds of organic compounds and a substance that can convert triplet excitation energy into luminescence. Note that light emitted from the first light-emitting layer has an emission peak on the shorter wavelength side than light emitted from the second light-emitting layer.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Takahiro ISHISONE, Satoshi SEO, Yusuke NONAKA, Nobuharu OHSAWA
  • Publication number: 20190139783
    Abstract: A semiconductor device having high reliability is provided.
    Type: Application
    Filed: April 11, 2017
    Publication date: May 9, 2019
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Yuji EGI, Noritaka ISHIHARA, Yusuke NONAKA, Yasumasa YAMANE, Ryo TOKUMARU, Daisuke MATSUBAYASHI
  • Publication number: 20190123290
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 25, 2019
    Inventors: Satoshi SEO, Takahiro ISHISONE, Nobuharu OHSAWA, Yusuke NONAKA, Toshiki SASAKI
  • Patent number: 10229338
    Abstract: An image processing method includes: identifying a dark region by binarizing an image captured using an imaging device; generating a line image of the dark region by thinning the dark region; identifying a first multiple pairs of pixels that are included in a pixel group forming the generated line image and are separated from each other by a predetermined threshold or more; calculating a first variance of gradients of lines connecting the respective pairs in the first plurality of pairs; identifying a second plurality of pairs of pixels that are included in the pixel group forming the generated line image and are separated from each other by values smaller than the predetermined threshold; calculating a second variance of gradients of lines connecting the respective pairs in the second plurality of pairs; and evaluating the dark region based on the first variance and the second variance.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: March 12, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yusuke Nonaka, Eigo Segawa