Patents by Inventor Yusuke Terada

Yusuke Terada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9360074
    Abstract: The present invention provides a wave spring and a load adjusting method therefor in which a ratio of a spring constant can be freely adjusted. In a wave spring, a high mountain portion and a low mountain portion form a combination, and the combination is repeatedly formed along a circumferential direction. A valley portion is formed between the mountain portions. Since distance between mountain portions is constant in the conventional design of wave springs, the ratios of spring constant are only specific values (plot indicated by ?). In contrast, in the design of the wave spring, since the pitch angle A of the high mountain portion and the pitch angle B of the low mountain portion can be changed in the combination, the ratio can be freely adjusted.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 7, 2016
    Assignee: NHK Spring Co., Ltd.
    Inventor: Yusuke Terada
  • Publication number: 20160141643
    Abstract: A deformation absorption member for a fuel-cell-stack disposed between an anode side separator and a cathode side separator. The deformation absorption member includes a thin-board-like base material, and a plurality of raised pieces in which extension portions extended from proximal ends are arranged in a grid pattern. Each raised piece of the plurality of raised pieces is formed in a non-rectangular shape in which the width of the extension portion is shorter than the width of the proximal end, and plurality of raised pieces are configured so that the directions of the extension portions of mutually adjacent raised pieces are alternately arranged, and positions of the proximal ends of the mutually adjacent raised pieces are arranged in at least overlapping positions.
    Type: Application
    Filed: June 30, 2014
    Publication date: May 19, 2016
    Applicant: NHK Spring Co., Ltd.
    Inventors: Yosuke FUKUYAMA, Takeshi SHIOMI, Yusuke TERADA, Norihiro TAJIMA
  • Publication number: 20160133948
    Abstract: A fuel-cell-stack manufacturing method, includes arranging an extension portion extended from a proximal end of a raised piece on one surface of a base material disposed so as to abut at least one of a cathode side separator and the anode side separator, and setting an interval between the anode side separator and the cathode side separator along a lamination direction so that deformation of the raised piece exceeds an elastic deformation region and enters a plastic deformation region, and is also in a region in which the proximal end moved due to the deformation does not come in contact with the cathode side separator or the anode side separator.
    Type: Application
    Filed: June 2, 2014
    Publication date: May 12, 2016
    Inventors: Yosuke FUKUYAMA, Takeshi SHIOMI, Yusuke TERADA, Norihiro TAJIMA
  • Publication number: 20160027735
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Application
    Filed: October 6, 2015
    Publication date: January 28, 2016
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Publication number: 20150349354
    Abstract: A fuel cell stack has a stacked plurality of single cells. Each of the single cells has a membrane electrode assembly, and a pair of separators sandwiching the membrane electrode assembly therebetween. A cooling fluid channel where a cooling fluid flows is formed between adjacent single cells. The fuel cell stack further comprises a displacement absorbing member disposed in the cooling fluid channel to absorb a displacement between the single cells. The displacement absorbing member comprises a channel flow resistance reduction structure that reduces a channel flow resistance of the cooling fluid channel against the cooling fluid.
    Type: Application
    Filed: November 8, 2013
    Publication date: December 3, 2015
    Applicants: Nissan Motor Co., Ltd., NHK Spring Co., Ltd.
    Inventors: Yosuke FUKUYAMA, Keita IRITSUKI, Yusuke TERADA, Norihiro TAJIMA
  • Patent number: 9194440
    Abstract: A clutch apparatus is equipped with two clutch structures having a clutch drum therein. A driven plate and a piston are provided in the clutch drum of each clutch structure, and a primary coned disc spring and a secondary coned disc spring, which are ring-shaped, are provided between the driven plate and the piston. A flat portion is formed on an inner peripheral portion of a convex surface of the primary coned disc spring, and the flat portion can come into contact with a counter member first when a load is applied. A load in a flat condition due to elastic deformation is adjusted by the flat portion so as to be a desirable value. Blanks and of the primary coned disc spring and the secondary coned disc spring can be obtained from one sheet of material having the same thickness. In this case, the flat portion is formed by press forming on an inner peripheral portion of the blank in view of the shape thereof after bending forming is performed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: November 24, 2015
    Assignee: NHK SPRING CO., LTD.
    Inventors: Yusuke Terada, Shuji Ando
  • Patent number: 9184126
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 10, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Publication number: 20150155231
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Patent number: 9003661
    Abstract: A clutch apparatus is equipped with two clutch structures having a clutch drum therein. A driven plate and a piston are provided in the clutch drum of each clutch structure, and a primary coned disc spring and a secondary coned disc spring, which are ring-shaped, are provided between the driven plate and the piston. A flat portion 12 is formed on an inner peripheral portion of a convex surface of the primary coned disc spring 1, and the flat portion 12 can come into contact with a counter member first when a load is applied. A load in a flat condition due to elastic deformation is adjusted by the flat portion so as to be a desirable value. Blanks 1A and 2A of the primary coned disc spring and the secondary coned disc spring can be obtained from one sheet of material having the same thickness. In this case, the flat portion 12A is formed by press forming on an inner peripheral portion of the blank 1A in view of the shape thereof after bending forming is performed.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: April 14, 2015
    Assignee: NHK Spring Co., Ltd.
    Inventors: Yusuke Terada, Shuji Ando
  • Patent number: 8975127
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Publication number: 20150042025
    Abstract: The present invention provides a wave spring and a load adjusting method therefor in which a ratio of a spring constant can be freely adjusted. In a wave spring, a high mountain portion and a low mountain portion form a combination, and the combination is repeatedly formed along a circumferential direction. A valley portion is formed between the mountain portions. Since distance between mountain portions is constant in the conventional design of wave springs, the ratios of spring constant are only specific values (plot indicated by ?). In contrast, in the design of the wave spring, since the pitch angle A of the high mountain portion and the pitch angle B of the low mountain portion can be changed in the combination, the ratio can be freely adjusted.
    Type: Application
    Filed: March 12, 2013
    Publication date: February 12, 2015
    Inventor: Yusuke Terada
  • Publication number: 20140138205
    Abstract: A clutch apparatus is equipped with two clutch structures having a clutch drum therein. A driven plate and a piston are provided in the clutch drum of each clutch structure, and a primary coned disc spring and a secondary coned disc spring, which are ring-shaped, are provided between the driven plate and the piston. A flat portion is formed on an inner peripheral portion of a convex surface of the primary coned disc spring, and the flat portion can come into contact with a counter member first when a load is applied. A load in a flat condition due to elastic deformation is adjusted by the flat portion so as to be a desirable value. Blanks and of the primary coned disc spring and the secondary coned disc spring can be obtained from one sheet of material having the same thickness. In this case, the flat portion is formed by press forming on an inner peripheral portion of the blank in view of the shape thereof after bending forming is performed.
    Type: Application
    Filed: December 26, 2013
    Publication date: May 22, 2014
    Applicant: NHK SPRING CO., LTD.
    Inventors: Yusuke TERADA, Shuji ANDO
  • Publication number: 20140051219
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Application
    Filed: October 22, 2013
    Publication date: February 20, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yusuke TERADA, Shigeya TOYOKAWA, Atsushi MAEDA
  • Patent number: 8604526
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: December 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Publication number: 20120037965
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Application
    Filed: October 26, 2011
    Publication date: February 16, 2012
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Patent number: 8072035
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Publication number: 20100116612
    Abstract: A clutch apparatus is equipped with two clutch structures having a clutch drum therein. A driven plate and a piston are provided in the clutch drum of each clutch structure, and a primary coned disc spring and a secondary coned disc spring, which are ring-shaped, are provided between the driven plate and the piston. A flat portion 12 is formed on an inner peripheral portion of a convex surface of the primary coned disc spring 1, and the flat portion 12 can come into contact with a counter member first when a load is applied. A load in a flat condition due to elastic deformation is adjusted by the flat portion so as to be a desirable value. Blanks 1A and 2A of the primary coned disc spring and the secondary coned disc spring can be obtained from one sheet of material having the same thickness. In this case, the flat portion 12A is formed by press forming on an inner peripheral portion of the blank 1A in view of the shape thereof after bending forming is performed.
    Type: Application
    Filed: April 2, 2008
    Publication date: May 13, 2010
    Applicant: NHK SPRING CO. LTD.
    Inventors: Yusuke Terada, Shuji Ando
  • Publication number: 20080303968
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 11, 2008
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Patent number: 7335875
    Abstract: An optical branching unit according to the invention, has on a substrate, a light input part which inputs light, an optical branch which branches the light input to the light input part at a predetermined ratio, a light output part which guides the light branched by the optical branch to a predetermined position, and a dummy pattern which is provided on a substrate independently of an area provided with the light input part, optical branch and light output part, made of the same material as the light input part, optical branch and light output part, and defined to have an area, so that an occupation rate, or a ratio of the dummy pattern to the area of a substrate except the light input part, optical branch and light output part, is 70% or higher.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 26, 2008
    Assignee: Omron Corporation
    Inventors: Yusuke Terada, Yutaka Natsume
  • Patent number: 7221844
    Abstract: An optical waveguide circuit component according to the present invention is characterized by that a clad layer composed of quartz is provided on the surfaces of a substrate and core formed by quartz doped selectively on a quartz plate structure, and a lid or a cover member is fixed onto the clad layer by heat pressing. With this structure, it is possible to reduce the magnitude of a polarization-dependent loss (PDL) generated when the lid and clad layer are combined.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: May 22, 2007
    Assignee: Omron Corporation
    Inventors: Fumio Takahashi, Fumitaka Yoshino, Yusuke Terada, Yutaka Natsume