Patents by Inventor Yusuke Terada

Yusuke Terada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070086711
    Abstract: An optical branching unit according to the invention, has on a substrate, a light input part which inputs light, an optical branch which branches the light input to the light input part at a predetermined ratio, a light output part which guides the light branched by the optical branch to a predetermined position, and a dummy pattern which is provided on a substrate independently of an area provided with the light input part, optical branch and light output part, made of the same material as the light input part, optical branch and light output part, and defined to have an area, so that an occupation rate, or a ratio of the dummy pattern to the area of a substrate except the light input part, optical branch and light output part, is 70% or higher.
    Type: Application
    Filed: November 17, 2006
    Publication date: April 19, 2007
    Applicant: OMRON CORPORATION
    Inventors: Yusuke Terada, Yutaka Natsume
  • Publication number: 20060018589
    Abstract: An optical waveguide circuit component according to the present invention is characterized by that a clad layer composed of quartz is provided on the surfaces of a substrate and core formed by quartz doped selectively on a quartz plate structure, and a lid or a cover member is fixed onto the clad layer by heat pressing. With this structure, it is possible to reduce the magnitude of a polarization-dependent loss (PDL) generated when the lid and clad layer are combined.
    Type: Application
    Filed: September 26, 2005
    Publication date: January 26, 2006
    Applicant: NHK Spring Co., Ltd.
    Inventors: Fumio Takahashi, Fumitaka Yoshino, Yusuke Terada, Yutaka Natsume
  • Publication number: 20040157358
    Abstract: A group III nitride semiconductor film involving few lattice defects and having a large thickness, and a process for making the film are disclosed. Dry-etching is conducted while a quartz substrate and a group III nitride semiconductor are placed on the top of a lower electrode. Nano-pillars (50) are formed on the top of the group III nitride semiconductor (101). Another group III nitride semiconductor film (51) is deposited on the nano-pillars (50).
    Type: Application
    Filed: April 1, 2004
    Publication date: August 12, 2004
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Harumasa Yoshida, Tatsuhiro Urushido, Yusuke Terada