Patents by Inventor Yusuke Tokunaga

Yusuke Tokunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10371026
    Abstract: An improved blow-by gas return structure minimizes the occurrence of a drawback caused by freezing at a low temperature by bringing a state where freezing minimally occurs in a blow-bay gas passage such as a pipe disposed outside an engine. The blow-by gas return structure is configured such that a blow-by gas is introduced into an intake manifold through an inner passage formed in a head cover. The blow-by gas return structure includes an outer pipe which connects a blow-by gas outlet of the head cover and a blow-by gas inlet of a main pipe of the intake manifold in a communicable manner, and a temperature elevating mechanism configured to elevate a temperature of the blow-by gas inlet. The temperature elevating mechanism is configured such that a cooling water transfer passage is formed in a portion of the blow-by gas inlet of the main pipe.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: August 6, 2019
    Assignee: KUBOTA Corporation
    Inventors: Takahiro Tokunaga, Yusuke Tanimoto, Kazuya Hamada, Shinji Kishi, Yuzo Umeda
  • Publication number: 20190152953
    Abstract: The present invention provides a compound of general formula (I) (wherein, R1, X, p and q are as described in the present description and claims), or a pharmacologically acceptable salt thereof, and a pharmaceutical composition containing that compound.
    Type: Application
    Filed: August 5, 2016
    Publication date: May 23, 2019
    Applicant: UBE INDUSTRIES, LTD.
    Inventors: Ken-ichi KOMORI, Akishi NINOMIYA, Shigeru USHIYAMA, Masaru SHINOHARA, Koji ITO, Tetsuo KAWAGUCHI, Yasunori TOKUNAGA, Hiroyoshi KAWADA, Haruka YAMADA, Yusuke SHIRAISHI, Masahiro KOJIMA, Masaaki ITO, Tomio KIMURA
  • Patent number: 10070089
    Abstract: An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 4, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yusuke Tokunaga
  • Patent number: 10049761
    Abstract: To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a ?-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: August 14, 2018
    Assignee: RIKEN
    Inventors: Yusuke Tokunaga, Xiuzhen Yu, Yasujiro Taguchi, Yoshinori Tokura, Yoshio Kaneko
  • Patent number: 10008282
    Abstract: To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a ?-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: June 26, 2018
    Assignee: RIKEN
    Inventors: Yusuke Tokunaga, Xiuzhen Yu, Yasujiro Taguchi, Yoshinori Tokura, Yoshio Kaneko
  • Publication number: 20170272674
    Abstract: An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 21, 2017
    Inventor: Yusuke TOKUNAGA
  • Publication number: 20170178747
    Abstract: To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a ?-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.
    Type: Application
    Filed: March 5, 2017
    Publication date: June 22, 2017
    Inventors: Yusuke TOKUNAGA, Xiuzhen YU, Yasujiro TAGUCHI, Yoshinori TOKURA, Yoshio KANEKO
  • Patent number: 9491385
    Abstract: A switched capacitor circuit includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; an inverting amplifier including a second input terminal connected to the second terminal; a capacitor including a third terminal, a fourth terminal, and a fifth terminal which is connected to an output terminal; a capacitor including a seventh terminal, a sixth terminal connected to the second output terminal, and an eighth terminal connected to the third terminal; a capacitor connected in series between the second terminal and the output terminal; and an offset compensation unit which outputs an offset voltage having a value of a short-circuit voltage of the inverting amplifier to the fourth terminal and the seventh terminal.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 8, 2016
    Assignee: PANASONIC CORPORATION
    Inventor: Yusuke Tokunaga
  • Patent number: 9368231
    Abstract: A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 14, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yusuke Tokunaga
  • Patent number: 9258503
    Abstract: An A/D converter includes: an A/D converter circuit that causes a dissipation current (Idis) having dependence on an input voltage (Vin); and a counteracting current generation circuit controlled based on an output digital value (Dout) provided from the A/D converter circuit to generate a counteracting current (Icnt) that is a dissipation current for reducing the dependence of the dissipation current (Idis) on the input voltage.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: February 9, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Tokunaga, Yasuhiro Tatewaki
  • Publication number: 20160037108
    Abstract: A switched capacitor circuit includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; an inverting amplifier including a second input terminal connected to the second terminal; a capacitor including a third terminal, a fourth terminal, and a fifth terminal which is connected to an output terminal; a capacitor including a seventh terminal, a sixth terminal connected to the second output terminal, and an eighth terminal connected to the third terminal; a capacitor connected in series between the second terminal and the output terminal; and an offset compensation unit which outputs an offset voltage having a value of a short-circuit voltage of the inverting amplifier to the fourth terminal and the seventh terminal.
    Type: Application
    Filed: June 25, 2015
    Publication date: February 4, 2016
    Inventor: Yusuke TOKUNAGA
  • Publication number: 20150255173
    Abstract: A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.
    Type: Application
    Filed: September 27, 2013
    Publication date: September 10, 2015
    Inventor: Yusuke Tokunaga
  • Publication number: 20150249801
    Abstract: An A/D converter includes: an A/D converter circuit that causes a dissipation current (Idis) having dependence on an input voltage (Vin); and a counteracting current generation circuit controlled based on an output digital value (Dout) provided from the A/D converter circuit to generate a counteracting current (Icnt) that is a dissipation current for reducing the dependence of the dissipation current (Idis) on the input voltage.
    Type: Application
    Filed: September 17, 2013
    Publication date: September 3, 2015
    Inventors: Yusuke Tokunaga, Yasuhiro Tatewaki
  • Patent number: 8912941
    Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Panasonic Corporation
    Inventor: Yusuke Tokunaga
  • Patent number: 8810959
    Abstract: A rotating device includes a rotor including a hub to receive a recording disk, and a fixed body including a base that fixedly supports a bearing unit to rotatably support the rotor. The fixed body includes a core having a cylindrical part and salient poles extending in a radial direction, a ring-shaped member having a core holding part that has the core fixed to an outer peripheral surface thereof, a sloping part extending in a direction inclined with respect to a rotational axis of the rotor from a side of the core holding part farther away from the hub, and a support part extending from a side of the sloping part farther away from the hub.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.
    Inventors: Yusuke Tokunaga, Tomoya Takahashi, Kazuyoshi Nagai
  • Publication number: 20140146416
    Abstract: A rotating device includes a rotor including a hub to receive a recording disk, and a fixed body including a base that fixedly supports a bearing unit to rotatably support the rotor. The fixed body includes a core having a cylindrical part and salient poles extending in a radial direction, a ring-shaped member having a core holding part that has the core fixed to an outer peripheral surface thereof, a sloping part extending in a direction inclined with respect to a rotational axis of the rotor from a side of the core holding part farther away from the hub, and a support part extending from a side of the sloping part farther away from the hub.
    Type: Application
    Filed: September 10, 2013
    Publication date: May 29, 2014
    Applicant: Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.
    Inventors: Yusuke TOKUNAGA, Tomoya Takahashi, Kazuyoshi Nagai
  • Publication number: 20140077985
    Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.
    Type: Application
    Filed: February 21, 2013
    Publication date: March 20, 2014
    Inventor: Yusuke Tokunaga
  • Patent number: 8508269
    Abstract: An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 13, 2013
    Assignee: Panasonic Corporation
    Inventors: Yusuke Tokunaga, Shiro Sakiyama
  • Patent number: 8390953
    Abstract: The disk drive device includes a base plate, a hub on which a recording disk is mounted, a shaft bearing unit that is arranged on the base plate and that rotatably supports the hub, and a spindle drive unit that drives the hub to rotate. The spindle driving unit includes a stator core having a salient pole, a coil wound around the salient pole, and a magnet opposed to the salient pole. The hub formed of a magnetic material includes an outer cylindrical portion engaged with an inner circumference of the recording disk. A shaft is inserted into a sleeve, and the sleeve, which is of an approximate cylindrical shape, is inserted into a housing as part of the shaft bearing unit. The shaft is fixed to the rotational center of the hub, rotating along the axis together with the hub.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: March 5, 2013
    Assignee: Alphana Technology Co., Ltd.
    Inventor: Yusuke Tokunaga
  • Publication number: 20130009796
    Abstract: A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: Panasonic Corporation
    Inventors: Shiro Sakiyama, Akinori Matsumoto, Yusuke Tokunaga, Ichiro Kuwabara