Patents by Inventor Yusuke Tokunaga
Yusuke Tokunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9368231Abstract: A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.Type: GrantFiled: September 27, 2013Date of Patent: June 14, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Yusuke Tokunaga
-
Patent number: 9258503Abstract: An A/D converter includes: an A/D converter circuit that causes a dissipation current (Idis) having dependence on an input voltage (Vin); and a counteracting current generation circuit controlled based on an output digital value (Dout) provided from the A/D converter circuit to generate a counteracting current (Icnt) that is a dissipation current for reducing the dependence of the dissipation current (Idis) on the input voltage.Type: GrantFiled: September 17, 2013Date of Patent: February 9, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yusuke Tokunaga, Yasuhiro Tatewaki
-
Publication number: 20160037108Abstract: A switched capacitor circuit includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; an inverting amplifier including a second input terminal connected to the second terminal; a capacitor including a third terminal, a fourth terminal, and a fifth terminal which is connected to an output terminal; a capacitor including a seventh terminal, a sixth terminal connected to the second output terminal, and an eighth terminal connected to the third terminal; a capacitor connected in series between the second terminal and the output terminal; and an offset compensation unit which outputs an offset voltage having a value of a short-circuit voltage of the inverting amplifier to the fourth terminal and the seventh terminal.Type: ApplicationFiled: June 25, 2015Publication date: February 4, 2016Inventor: Yusuke TOKUNAGA
-
Publication number: 20150255173Abstract: A switched capacitor circuit according to the present invention includes: a capacitor including a first terminal to which the input voltage is applied and a second terminal; a capacitor including a third terminal and a fourth terminal; an inverting amplifier including a second output terminal and a second input terminal which is connected to the fourth terminal; a capacitor including a fifth terminal and a sixth terminal; a capacitor including a seventh terminal and an eighth terminal and included in an electrical path between the second output terminal and the fifth terminal; and a capacitor including a ninth terminal and a tenth terminal connected to the second terminal and the sixth terminal, respectively. The third terminal is connected to the second terminal. The sixth terminal is connected to the output terminal.Type: ApplicationFiled: September 27, 2013Publication date: September 10, 2015Inventor: Yusuke Tokunaga
-
Publication number: 20150249801Abstract: An A/D converter includes: an A/D converter circuit that causes a dissipation current (Idis) having dependence on an input voltage (Vin); and a counteracting current generation circuit controlled based on an output digital value (Dout) provided from the A/D converter circuit to generate a counteracting current (Icnt) that is a dissipation current for reducing the dependence of the dissipation current (Idis) on the input voltage.Type: ApplicationFiled: September 17, 2013Publication date: September 3, 2015Inventors: Yusuke Tokunaga, Yasuhiro Tatewaki
-
Patent number: 8912941Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.Type: GrantFiled: February 21, 2013Date of Patent: December 16, 2014Assignee: Panasonic CorporationInventor: Yusuke Tokunaga
-
Patent number: 8810959Abstract: A rotating device includes a rotor including a hub to receive a recording disk, and a fixed body including a base that fixedly supports a bearing unit to rotatably support the rotor. The fixed body includes a core having a cylindrical part and salient poles extending in a radial direction, a ring-shaped member having a core holding part that has the core fixed to an outer peripheral surface thereof, a sloping part extending in a direction inclined with respect to a rotational axis of the rotor from a side of the core holding part farther away from the hub, and a support part extending from a side of the sloping part farther away from the hub.Type: GrantFiled: September 10, 2013Date of Patent: August 19, 2014Assignee: Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.Inventors: Yusuke Tokunaga, Tomoya Takahashi, Kazuyoshi Nagai
-
Publication number: 20140146416Abstract: A rotating device includes a rotor including a hub to receive a recording disk, and a fixed body including a base that fixedly supports a bearing unit to rotatably support the rotor. The fixed body includes a core having a cylindrical part and salient poles extending in a radial direction, a ring-shaped member having a core holding part that has the core fixed to an outer peripheral surface thereof, a sloping part extending in a direction inclined with respect to a rotational axis of the rotor from a side of the core holding part farther away from the hub, and a support part extending from a side of the sloping part farther away from the hub.Type: ApplicationFiled: September 10, 2013Publication date: May 29, 2014Applicant: Samsung Electro-Mechanics Japan Advanced Technology Co., Ltd.Inventors: Yusuke TOKUNAGA, Tomoya Takahashi, Kazuyoshi Nagai
-
Publication number: 20140077985Abstract: An analog-to-digital conversion circuit includes: a clock generating circuit which generates a clock signal including a first initial period and plural normal periods following the first initial period, the first initial period being one of a high period and a low period and being a first period immediately after a reset release, each of the normal periods being one of a high period and a low period and shorter than the first initial period; and an incremental analog-to-digital converter which operates using the clock signal.Type: ApplicationFiled: February 21, 2013Publication date: March 20, 2014Inventor: Yusuke Tokunaga
-
Patent number: 8508269Abstract: An oscillator circuit complementarily increases or reduces, in response to a transition of a signal level of a reference clock, a signal level of a first oscillation signal and a signal level of a second oscillation signal. An oscillation control circuit compares the first and second oscillation signals to a comparison voltage, and transitions the signal level of the reference clock in accordance with a result of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced. A reference voltage control circuit increases or reduces the reference voltage according to a frequency difference between a basis clock and the reference clock.Type: GrantFiled: December 21, 2012Date of Patent: August 13, 2013Assignee: Panasonic CorporationInventors: Yusuke Tokunaga, Shiro Sakiyama
-
Patent number: 8390953Abstract: The disk drive device includes a base plate, a hub on which a recording disk is mounted, a shaft bearing unit that is arranged on the base plate and that rotatably supports the hub, and a spindle drive unit that drives the hub to rotate. The spindle driving unit includes a stator core having a salient pole, a coil wound around the salient pole, and a magnet opposed to the salient pole. The hub formed of a magnetic material includes an outer cylindrical portion engaged with an inner circumference of the recording disk. A shaft is inserted into a sleeve, and the sleeve, which is of an approximate cylindrical shape, is inserted into a housing as part of the shaft bearing unit. The shaft is fixed to the rotational center of the hub, rotating along the axis together with the hub.Type: GrantFiled: March 21, 2012Date of Patent: March 5, 2013Assignee: Alphana Technology Co., Ltd.Inventor: Yusuke Tokunaga
-
Publication number: 20130009796Abstract: A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: Panasonic CorporationInventors: Shiro Sakiyama, Akinori Matsumoto, Yusuke Tokunaga, Ichiro Kuwabara
-
Publication number: 20120319880Abstract: A controller controls first and second supply switches so that, during a sampling period, a ground voltage is supplied to n first up-capacitors and n second up-capacitors while a power supply voltage is supplied to n first down-capacitors and n second down-capacitors. The controller also controls the first and second supply switches based on the result of comparison by a comparator during each of n bit determination periods so that a first analog voltage at a first sampling node and a second analog voltage at a second sampling node gradually approach each other.Type: ApplicationFiled: August 29, 2012Publication date: December 20, 2012Applicant: Panasonie CorporationInventors: Akinori MATSUMOTO, Shiro SAKIYAMA, Yusuke TOKUNAGA, Ichiro KUWABARA
-
Publication number: 20120176879Abstract: The disk drive device includes a base plate, a hub on which a recording disk is mounted, a shaft bearing unit that is arranged on the base plate and that rotatably supports the hub, and a spindle drive unit that drives the hub to rotate. The spindle driving unit includes a stator core having a salient pole, a coil wound around the salient pole, and a magnet opposed to the salient pole. The hub formed of a magnetic material includes an outer cylindrical portion engaged with an inner circumference of the recording disk. A shaft is inserted into a sleeve, and the sleeve, which is of an approximate cylindrical shape, is inserted into a housing as part of the shaft bearing unit. The shaft is fixed to the rotational center of the hub, rotating along the axis together with the hub.Type: ApplicationFiled: March 21, 2012Publication date: July 12, 2012Applicant: ALPHANA TECHNOLOGY CO., LTD.Inventor: Yusuke TOKUNAGA
-
Patent number: 8212624Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.Type: GrantFiled: February 7, 2011Date of Patent: July 3, 2012Assignee: Panasonic CorporationInventors: Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho
-
Patent number: 8184396Abstract: The disk drive device includes a base plate, a hub on which a recording disk is mounted, a shaft bearing unit that is arranged on the base plate and that rotatably supports the hub, and a spindle drive unit that drives the hub to rotate. The spindle driving unit includes a stator core having a salient pole, a coil wound around the salient pole, and a magnet opposed to the salient pole. The hub formed of a magnetic material includes an outer cylindrical portion engaged with an inner circumference of the recording disk. A shaft is inserted into a sleeve, and the sleeve, which is of an approximate cylindrical shape, is inserted into a housing as part of the shaft bearing unit. The shaft is fixed to the rotational center of the hub, rotating along the axis together with the hub.Type: GrantFiled: September 2, 2009Date of Patent: May 22, 2012Assignee: Alphana Technology Co., Ltd.Inventor: Yusuke Tokunaga
-
Patent number: 8130608Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.Type: GrantFiled: December 14, 2010Date of Patent: March 6, 2012Assignee: Panasonic CorporationInventors: Akinori Matsumoto, Shiro Sakiyama, Shiro Dosho, Yusuke Tokunaga, Takashi Morie
-
Patent number: 8040168Abstract: The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.Type: GrantFiled: July 26, 2005Date of Patent: October 18, 2011Assignee: Panasonic CorporationInventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Toru Iwata, Takashi Hirata
-
Patent number: 8013650Abstract: A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.Type: GrantFiled: September 1, 2006Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Shiro Dosho, Shiro Sakiyama, Yusuke Tokunaga, Seiji Watanabe, Hiroshi Koshida
-
Publication number: 20110140754Abstract: An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.Type: ApplicationFiled: February 7, 2011Publication date: June 16, 2011Applicant: PANASONIC CORPORATIONInventors: Yusuke TOKUNAGA, Shiro SAKIYAMA, Akinori MATSUMOTO, Shiro DOSHO