Patents by Inventor Yuta Yoshida
Yuta Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10424575Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.Type: GrantFiled: March 26, 2015Date of Patent: September 24, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
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Patent number: 10388366Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: GrantFiled: May 16, 2018Date of Patent: August 20, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20190193199Abstract: A laser processing apparatus includes a laser oscillator oscillating a laser beam, a light condensing lens condensing the laser beam oscillated by the laser oscillator, and a mask member disposed between the laser oscillator and the light condensing lens and blocking part of the laser beam oscillated by the laser oscillator, in which the mask member includes a transmitting portion through which light passes, and a reflecting film surrounding the transmitting portion and reflecting the part of the laser beam.Type: ApplicationFiled: December 5, 2018Publication date: June 27, 2019Inventor: Yuta YOSHIDA
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Patent number: 10211104Abstract: A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral surplus region, a holding step of holding the package wafer in such a manner that the grooves are exposed, an orientation adjustment step of causing the grooves to be parallel to a processing-feed direction in which processing feeding of a chuck table is carried out when dividing grooves are formed, a coordinate registration step of imaging both ends of the plural grooves exposed at a peripheral edge and registering coordinate information of both ends or a single side of the grooves from taken images, and a dividing groove forming step of calculating the positions of the dividing grooves to be formed along the grooves based on the registered coordinate information of the grooves and forming the dividing grooves along the grooves.Type: GrantFiled: August 15, 2017Date of Patent: February 19, 2019Assignee: Disco CorporationInventors: Yuta Yoshida, Hironari Ohkubo
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Patent number: 10198826Abstract: The present invention provides a method for accurately and simply measuring a blade width (W) of a blade tip section (1) of a grooving tool mounted on a machine tool.Type: GrantFiled: July 31, 2017Date of Patent: February 5, 2019Assignee: O-M LTD.Inventors: Hiroki Inui, Dai Ito, Hirofumi Nakakubo, Katsunori Kabasawa, Yuta Yoshida
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Publication number: 20180261280Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Applicant: Renesas Electronics CorporationInventors: Shinji TANAKA, Makoto YABUUCHI, Yuta YOSHIDA
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Publication number: 20180214986Abstract: A laser processing apparatus includes: a chuck table that holds a packaged wafer by a holding surface; a laser processing unit that applies a laser beam to the packaged wafer to form a through-groove along each division line; an X-axis moving unit that moves the chuck table in an X-axis direction; and an examination unit. The chuck table includes: a holding member that forms the holding surface; and a light emitting body. The examination unit includes: a line sensor that extends in a Y-axis direction; and a control unit that determines the result of processing through reception by the line sensor of light from the light emitting body through the through-groove. The line sensor images the whole surface of the packaged wafer being held by the chuck table.Type: ApplicationFiled: January 26, 2018Publication date: August 2, 2018Inventors: Yuri Ban, Yuta Yoshida, Kentaro Odanaka
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Publication number: 20180211852Abstract: A laser processing apparatus includes: a chuck table that holds a packaged wafer; a laser beam applying unit that applies a pulsed laser beam to the packaged wafer; X-axis moving unit for moving the chuck table in an X-axis direction; an imaging unit that images the packaged wafer; and a control unit. The chuck table has a transparent or semi-transparent holding member and a light emitting body. The control unit includes: an imaging instruction section that causes the imaging unit to image the packaged wafer while the pulsed laser beam is being applied to the packaged wafer; and a determination section that determines the processed state of a through-groove from a picked-up image obtained according to an instruction by the imaging instruction section.Type: ApplicationFiled: January 23, 2018Publication date: July 26, 2018Inventors: Yuri Ban, Yuta Yoshida, Kentaro Odanaka
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Patent number: 10002662Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: GrantFiled: September 27, 2017Date of Patent: June 19, 2018Assignee: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20180061711Abstract: A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral surplus region, a holding step of holding the package wafer in such a manner that the grooves are exposed, an orientation adjustment step of causing the grooves to be parallel to a processing-feed direction in which processing feeding of a chuck table is carried out when dividing grooves are formed, a coordinate registration step of imaging both ends of the plural grooves exposed at a peripheral edge and registering coordinate information of both ends or a single side of the grooves from taken images, and a dividing groove forming step of calculating the positions of the dividing grooves to be formed along the grooves based on the registered coordinate information of the grooves and forming the dividing grooves along the grooves.Type: ApplicationFiled: August 15, 2017Publication date: March 1, 2018Inventors: Yuta Yoshida, Hironari Ohkubo
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Publication number: 20180053317Abstract: The present invention provides a method for accurately and simply measuring a blade width (W) of a blade tip section (1) of a grooving tool mounted on a machine tool.Type: ApplicationFiled: July 31, 2017Publication date: February 22, 2018Applicant: O-M LTD.Inventors: Hiroki INUI, Dai ITO, Hirofumi NAKAKUBO, Katsunori KABASAWA, Yuta YOSHIDA
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Publication number: 20180019013Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: September 27, 2017Publication date: January 18, 2018Applicant: RENESAS ELECTRONICS CORPORATIONInventors: SHINJI TANAKA, MAKOTO YABUUCHI, YUTA YOSHIDA
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Patent number: 9831381Abstract: A package substrate machining method is provided. The package substrate includes a ceramic substrate, a plurality of device chips arranged on one face of the ceramic substrate, and a coating layer made of a resin that covers the entire one face of the ceramic substrate. The package substrate machining method includes a first laser-machined groove formation step adapted to form, in the coating layer, first laser-machined grooves along scheduled division lines set up on the package substrate by irradiating a laser beam at a wavelength absorbable by the coating layer from the coating layer side of the package substrate; and a second laser-machined groove formation step adapted to form, in the ceramic substrate and after the first laser-machined groove formation step, second laser-machined grooves along the scheduled division lines by irradiating a laser beam from the ceramic substrate side of the package substrate.Type: GrantFiled: August 26, 2016Date of Patent: November 28, 2017Assignee: Disco CorporationInventor: Yuta Yoshida
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Publication number: 20170338118Abstract: A laser processing apparatus has a laser beam applying unit for applying a laser beam to a workpiece held on a chuck table. The laser beam applying unit includes an elliptical spot forming member for changing the spot shape of a pulsed laser beam into an elliptical shape and making the major axis of the elliptical beam spot parallel to a feeding direction, a diffractive optical element for branching the pulsed laser beam having the elliptical beam spot obtained by the elliptical spot forming member, into a plurality of pulsed laser beams each having an elliptical beam spot whose major axis extends in the feeding direction, and a condensing lens for condensing each of the pulsed laser beams branched by the diffractive optical element to the workpiece in such a manner that the major axes of the elliptical beam spots of the pulsed laser beams branched are partially overlapped.Type: ApplicationFiled: May 11, 2017Publication date: November 23, 2017Inventor: Yuta Yoshida
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Patent number: 9799396Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: GrantFiled: December 2, 2016Date of Patent: October 24, 2017Assignee: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20170301664Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.Type: ApplicationFiled: March 26, 2015Publication date: October 19, 2017Inventors: Yuta YOSHIDA, Makoto YABUUCHI, Yoshisato YOKOYAMA
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Publication number: 20170084327Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Applicant: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20170077347Abstract: A package substrate machining method is provided. The package substrate includes a ceramic substrate, a plurality of device chips arranged on one face of the ceramic substrate, and a coating layer made of a resin that covers the entire one face of the ceramic substrate. The package substrate machining method includes a first laser-machined groove formation step adapted to form, in the coating layer, first laser-machined grooves along scheduled division lines set up on the package substrate by irradiating a laser beam at a wavelength absorbable by the coating layer from the coating layer side of the package substrate; and a second laser-machined groove formation step adapted to form, in the ceramic substrate and after the first laser-machined groove formation step, second laser-machined grooves along the scheduled division lines by irradiating a laser beam from the ceramic substrate side of the package substrate.Type: ApplicationFiled: August 26, 2016Publication date: March 16, 2017Inventor: Yuta Yoshida
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Patent number: 9542999Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: GrantFiled: December 28, 2015Date of Patent: January 10, 2017Assignee: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20160133315Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Applicant: Renesas Electronics CorporationInventors: Shinji TANAKA, Makoto YABUUCHI, Yuta YOSHIDA