Patents by Inventor Yuta Yoshida

Yuta Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9284657
    Abstract: A replenisher which is capable of supplying Zr ions to a metal surface treatment solution, while suppressing an increase in the HF concentration in the metal surface treatment solution, so that a chemical conversion coating film can be continuously formed on a steel sheet by electrolysis and contains (A) zirconium hydrofluoric acid or a salt thereof and/or (B) hydrofluoric acid or a salt thereof and (C) a fluorine-free zirconium compound. The total concentration (g/l) of zirconium ions derived from the components (A) and (C) is 20 or more, and the ratio of the total molar amount (MF) of the fluorine ions derived from the components (A) and (B) relative to the total molar amount (MZr) of the zirconium ions derived from the components (A) and (C), namely MF/MZr is 0.01 or more but less than 4.00.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 15, 2016
    Assignee: NIHON PARKERIZING CO., LTD.
    Inventors: Yuta Yoshida, Hiroki Sunada, Shigeki Yamamoto, Hidehiro Yamaguchi
  • Patent number: 9281017
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: March 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 9251862
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 9099640
    Abstract: Electrodes (7, 8, 9), having curved sections in the shape of the outline thereof, are disposed in areas of a rectangular plate-shaped piezoelectric transducer element (1) in which the strain in the natural mode of vibration is large. The electrodes (7, 8) which excite a bending vibration are disposed in areas in which the strain in the bending natural mode is at least a predetermined value, and the outline curved sections of the electrodes (7, 8) are shaped so as to follow along strain contours (3, 4), and the electrode (9) which excites a stretching vibration is disposed in an area in which the strain in the stretching natural mode is at least a predetermined value, thus providing a transducer for an ultrasonic motor which aims to reduce transducer loss (increasing vibration efficiency), and improve transducer durability and reliability.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: August 4, 2015
    Assignees: ISHIKAWA PREFECTURE, NIKKO COMPANY, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Masahiro Takano, Kenichi Hirosaki, Yuta Yoshida, Takuya Nagata, Shou Makino, Satoru Ichimura, Takashi Yoshida, Masayuki Ishida, Hiroshi Kawai, Mikio Takimoto, Kentaro Nakamura
  • Publication number: 20150021192
    Abstract: The purpose of the present invention is to provide a replenisher which is capable of supplying Zr ions to a metal surface treatment solution, while suppressing an increase in the HF concentration in the metal surface treatment solution, so that a chemical conversion coating film can be continuously formed on a steel sheet by electrolysis. A replenisher of the present invention is a replenisher which is used for the purpose of supplying zirconium ions to a metal surface treatment solution that contains zirconium ions and fluorine ions, and the replenisher contains (A) zirconium hydrofluoric acid or a salt thereof and/or (B) hydrofluoric acid or a salt thereof and (C) a fluorine-free zirconium compound.
    Type: Application
    Filed: November 30, 2011
    Publication date: January 22, 2015
    Inventors: Yuta Yoshida, Hiroki Sunada, Shigeki Yamamoto, Hidehiro Yamaguchi
  • Publication number: 20140313811
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventors: Shinji TANAKA, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 8797781
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Publication number: 20140016391
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shinji TANAKA, Makoto YABUUCHI, Yuta YOSHIDA
  • Patent number: 8619829
    Abstract: The present invention provides a semiconductor laser device including: a plurality of light emitting sections arranged in strip shapes in parallel; a plurality of first electrodes arranged along top faces of the light emitting sections, respectively; an insulating film covering a whole surface of the plurality of first electrodes, and including contact apertures corresponding to the first electrodes, respectively; a plurality of second electrodes arranged in positions different from those of the plurality of light emitting sections, correspondingly to the first electrodes; a plurality of wiring layers arranged on the insulating layer, and electrically connecting the second electrodes and the corresponding first electrodes through the contact apertures, respectively; and a plurality of window regions arranged for the light emitting sections in the insulating film so as to expose the first electrodes, respectively, and including at least two window regions having areas different from each other.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 31, 2013
    Assignee: Sony Corporation
    Inventors: Yuta Yoshida, Sachio Karino, Takahiro Yokoyama, Makoto Nakashima, Eiji Takase
  • Patent number: 8619826
    Abstract: A laser diode includes: a plurality of strip-shaped laser structures arranged in parallel with each other, and including a lower cladding layer, an active layer, and an upper cladding layer in this order; a plurality of strip-shaped upper electrodes singly formed on a top face of the respective laser structures, and being electrically connected to the upper cladding layer; a plurality of wiring layers being at least singly and electrically connected to one of the respective upper electrodes; and a plurality of pad electrodes formed in a region different from that of the plurality of laser structures, and being electrically connected to one of the respective upper electrodes with the wiring layer in between. The respective wiring layers have an end in a region different from a region where the respective wiring layers are contacted with the upper electrode.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: December 31, 2013
    Assignee: Sony Corporation
    Inventors: Makoto Nakashima, Takahiro Yokoyama, Sachio Karino, Eiji Takase, Yuta Yoshida
  • Patent number: 8559290
    Abstract: An optical information recording/reproducing optical system where resin material has Tg>115° C., first, second and third films are on an optical disc side of an objective lens and surfaces of an optical element, respectively, a light source side of the objective lens has a fourth film having four or more layers not containing Ti, each of the first, second and third films includes a non-high refractive index layer made of one of silicon oxide, aluminum oxide, aluminum fluoride and magnesium fluoride or a mixture of at least two of them, each of the first, second and third films is not made of one of Ti, Ta, Hf, Zr, Nb, Mo and Cr, a layer of the fourth film closest to a base material is the non-high refractive index layer. The fourth film satisfies 350<?max(2)<420 and 600<?min(2)<750, and reflectivity thereof decreases monotonously.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 15, 2013
    Assignee: Hoya Corporation
    Inventors: Satoshi Inoue, Yuta Yoshida, Naoto Hashimoto, Suguru Takishima
  • Patent number: 8547723
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 8339925
    Abstract: An optical information recording/reproducing optical system, comprising a light source; an optical element converting a laser beam into a substantially collimated beam; and an objective lens, wherein a wavelength ? (unit: nm) of the laser beam falls within a range of 400<?<410, the optical element and the objective lens are made of same resin materials or different resin materials having a glass transition temperature of Tg>115° C., each of optical surfaces is configured not to have an optical thin film which contains at least one of or elements of titanium, tantalum, hafnium, zirconium, niobium, molybdenum and chromium, each of optical surfaces of the optical element is provided with an antireflection film made of one of or a mixture of at least two of silicon oxide, aluminum oxide, aluminum fluoride and magnesium fluoride, and a following condition is satisfied ? i = 1 n - 1 ? ( 1 - R ( BL ) ? i 100 ) - ? i = 1 n - 1 ? ( 1 - R ( UV ) ? i 100 ) > 0.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 25, 2012
    Assignee: Hoya Corporation
    Inventors: Satoshi Inoue, Yuta Yoshida, Naoto Hashimoto, Suguru Takishima
  • Publication number: 20120314269
    Abstract: A piezoelectric actuator mechanism including: a screw-driven feeding mechanism that has a feed screw (11) and a feed screw nut (14); a disc-shaped rotor (17) mounted on the rear-end face of the feed screw nut (14); an ultrasonic motor (18) having a piezoelectric vibrator (19) that comes in contact with the circumference face of the rotor (17); and a driven mounting portion that is pressed against the leading end of the feed screw 11 by spring force, and displaced and positioned by the feeding operation of the feed screw. The driven mounting portion can be made to be a mirror holder (1) for use in an optical system, or a movable table (21) of a linear stage.
    Type: Application
    Filed: January 26, 2011
    Publication date: December 13, 2012
    Applicants: ISHIKAWA PREFECTURE, TOKYO INSTITUTE OF TECHNOLOGY, NIKKO COMPANY, SIGMA KOKI CO., LTD
    Inventors: Masahiro Takano, Kenichi Hirosaki, Ryuji Shintani, Yuta Yoshida, Toshiharu Minamikawa, Kouichi Nakano, Takuya Nagata, Shou Makino, Satoru Ichimura, Takashi Yoshida, Masayuki Ishida, Hiroshi Kawai, Mikio Takimoto, Kentaro Nakamura
  • Publication number: 20120293043
    Abstract: Electrodes (7, 8, 9), having curved sections in the shape of the outline thereof, are disposed in areas of a rectangular plate-shaped piezoelectric transducer element (1) in which the strain in the natural mode of vibration is large. The eletrodes (7, 8) which excite a bending vibration are disposed in areas in which the strain in the bending natural mode is at least a predetermined value, and the outline curved sections of the electrodes (7, 8) are shaped so as to follow along strain contours (3, 4), and the electrode (9) which excites a stretching vibration is disposed in an area in which the strain in the stretching natural mode is at least a predetermined value, thus providing a transducer for an ultrasonic motor which aims to reduce transducer loss (increasing vibration efficiency), and improve transducer durability and reliability.
    Type: Application
    Filed: January 26, 2011
    Publication date: November 22, 2012
    Applicants: ISHIKAWA PREFECTURE, TOKYO INSTITUTE OF TECHNOLOGY, NIKKO COMPANY, SIGMA KOKI CO., LTD
    Inventors: Masahiro Takano, Kenichi Hirosaki, Yuta Yoshida, Takuya Nagata, Shou Makino, Satoru Ichimura, Takashi Yoshida, Masayuki Ishida, Hiroshi Kawai, Mikio Takimoto, Kentaro Nakamura
  • Patent number: 8305865
    Abstract: An objective lens for an optical information recording/reproducing optical system for an optical disc letting a laser beam impinge on a recording layer of the optical disc, and wherein a center wavelength ? (unit: nm) of the laser beam is in a range defined by a condition: 390???420, a base material of the objective lens is made of resin, the resin has a glass transition temperature Tg and light transmissivity T (unit: %) per a path length of 3 mm at a wavelength of 406 nm defined by conditions: Tg?115° C., 85?T?90, same antireflection films or different types of antireflection films are respectively formed on optical surfaces of the objective lens, and each of the antireflection films formed on the objective lens has a thickness of 100 nm or more in a vicinity of an optical axis of the objective lens.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: November 6, 2012
    Assignee: Hoya Corporation
    Inventors: Satoshi Inoue, Yuta Yoshida, Naoto Hashimoto, Suguru Takishima
  • Publication number: 20120224405
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: February 16, 2012
    Publication date: September 6, 2012
    Inventors: Shinji TANAKA, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 8223814
    Abstract: The present invention provides a semiconductor laser realizing reduced possibility that a wiring layer disposed in the air is broken even under severe environment of a large temperature difference. A trench is provided between adjacent ridges, and a wiring layer electrically connecting an upper electrode and a pad electrode is disposed in the air at least above the trench. The wiring layer in a portion above the trench has a flat shape or a concave shape which dents toward the trench. With the configuration, accumulation of strains in the wiring layer when the wiring layer repeats expansion and shrink under severe environment of a large temperature difference is suppressed.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: July 17, 2012
    Assignee: Sony Corporation
    Inventors: Hisayoshi Kuramochi, Tomonori Hino, Tatsuhiro Hirata, Yuta Yoshida
  • Publication number: 20110103217
    Abstract: An objective lens for an optical information recording/reproducing optical system for an optical disc letting a laser beam impinge on a recording layer of the optical disc, and wherein a center wavelength ? (unit: nm) of the laser beam is in a range defined by a condition: 390???420, a base material of the objective lens is made of resin, the resin has a glass transition temperature Tg and light transmissivity T (unit: %) per a path length of 3 mm at a wavelength of 406 nm defined by conditions: Tg?115° C., 85?T?90, same antireflection films or different types of antireflection films are respectively formed on optical surfaces of the objective lens, and each of the antireflection films formed on the objective lens has a thickness of 100 nm or more in a vicinity of an optical axis of the objective lens.
    Type: Application
    Filed: September 29, 2010
    Publication date: May 5, 2011
    Applicant: HOYA CORPORATION
    Inventors: Satoshi INOUE, Yuta YOSHIDA, Naoto HASHIMOTO, Suguru TAKISHIMA
  • Publication number: 20110075541
    Abstract: An optical information recording/reproducing optical system where resin material has Tg>115° C., first, second and third films are on an optical disc side of an objective lens and surfaces of an optical element, respectively, a light source side of the objective lens has a fourth film having four or more layers not containing Ti, each of the first, second and third films includes a non-high refractive index layer made of one of silicon oxide, aluminum oxide, aluminum fluoride and magnesium fluoride or a mixture of at least two of them, each of the first, second and third films is not made of one of Ti, Ta, Hf, Zr, Nb, Mo and Cr, a layer of the fourth film closest to a base material is the non-high refractive index layer. The fourth film satisfies 350<?max(2)<420 and 600<?min(2)<750, and reflectivity thereof decreases monotonously.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 31, 2011
    Applicant: HOYA CORPORATION
    Inventors: Satoshi INOUE, Yuta YOSHIDA, Naoto HASHIMOTO, Suguru TAKISHIMA