Patents by Inventor Yutaka Akiyama

Yutaka Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6686916
    Abstract: A method of creating a reference table where polygon elements and rectangular pieces are connected with each other. The processor searches, as first searched rectangular pieces, the rectangular pieces that include the vertexes of the target polygon element, so as to register the element number of the target polygon element for the rows corresponding to the first searched rectangular pieces. Then the processor searches, as second searched rectangular pieces, the rectangular pieces that are traversed by the edges of the target polygon element, so as to register the element number of the target polygon element for the rows corresponding to the second searched rectangular pieces. The processor further registers the element number of the target polygon element for the rows corresponding to the rectangular pieces that exist within the target polygon element, so that the element number of the target polygon element is registered with all of the rectangular pieces overlapping the target polygon element.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: February 3, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Yutaka Akiyama
  • Publication number: 20030235833
    Abstract: The object of the present invention is to provide a technique for efficiently extracting GPCR sequences from human genome sequences, thereby comprehensively identifying novel GPCRs. An original automatic system for identifying GPCR sequences is disclosed, and 1035 novel GPCRs are successfully identified from the entire human genome by utilizing the system.
    Type: Application
    Filed: November 13, 2002
    Publication date: December 25, 2003
    Applicant: National Institute of Advanced industrial Science and Technology
    Inventors: Makiko Suwa, Kiyoshi Asai, Yutaka Akiyama, Hiroyuki Aburatani
  • Publication number: 20030143668
    Abstract: The object of the present invention is to provide a technique for efficiently extracting GPCR sequences from human genome sequences, thereby comprehensively identifying novel GPCRs.
    Type: Application
    Filed: December 18, 2001
    Publication date: July 31, 2003
    Applicant: National Institute of Advanced Industrial
    Inventors: Makiko Suwa, Kiyoshi Asai, Yutaka Akiyama, Hiroyuki Aburatani
  • Patent number: 6513150
    Abstract: Region boundary line segments are acquired, and simplification values of mesh points on each of the region boundary line segments are calculated. The simplification value of a fixed mesh point is set to a value sufficiently larger than a reference simplification value. The mesh point whose simplification value is the smallest is selected from the mesh points on each region boundary line segment. If the simplification value of the selected mesh point is positive and smaller than the reference simplification value, then the simplification value of the selected mesh point is equally distributed to the mesh points on both sides of and adjacent to the selected mesh point, and the selected mesh point is deleted. The above process is repeated until the simplification values of all the mesh points in the region boundary line segments become greater than the reference simplification value.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: January 28, 2003
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 6349271
    Abstract: In a process simulating method for simulating an oxidation process of a semiconductor device manufacturing step, even when the respective elements of this semiconductor device own arbitrary shapes, a time step of an oxidizing agent diffusion within an oxide film can be properly calculated in the oxidation process.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: February 19, 2002
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Publication number: 20020007259
    Abstract: A method of creating a reference table where polygon elements and rectangular pieces are connected with each other. The processor searches, as first searched rectangular pieces, the rectangular pieces that include the vertexes of the target polygon element, so as to register the element number of the target polygon element for the rows corresponding to the first searched rectangular pieces. Then the processor searches, as second searched rectangular pieces, the rectangular pieces that are traversed by the edges of the target polygon element, so as to register the element number of the target polygon element for the rows corresponding to the second searched rectangular pieces. The processor further registers the element number of the target polygon element for the rows corresponding to the rectangular pieces that exist within the target polygon element, so that the element number of the target polygon element is registered with all of the rectangular pieces overlapping the target polygon element.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 17, 2002
    Applicant: NEC CORPORATION
    Inventor: Yutaka Akiyama
  • Patent number: 6313504
    Abstract: A vertical MOS semiconductor device in accordance with the present invention is provided with a semiconductor base; and a vertical MOS transistor having a well diffusion layer of a conductive type opposite to that of the semiconductor base, and a source diffusion layer of the same conductive type as that of the semiconductor base; wherein a channel length in a horizontal direction with respect to a main surface of the semiconductor base from a junction of the source diffusion layer to a junction of the well diffusion layer is set such that it is larger than a length at which a punch-through phenomenon takes place between the semiconductor base and the source diffusion layer and at which a minimum resistance value of the well diffusion layer is obtained. This arrangement makes it possible to reduce the size of the entire vertical MOS semiconductor device to 90% as compared with a conventional vertical MOS semiconductor device, without sacrificing a high breakdown voltage characteristic.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: November 6, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kenichi Furuta, Yutaka Akiyama, Osamu Kawai
  • Patent number: 6285970
    Abstract: A simulation method of Si oxidation is provided, which decreases the simulation time. A diffusion equation of oxidant is solved at individual nodes in a SiO2 region to calculate the surface concentration of the oxidant at the Si/SiO2 interface, resulting in the first value of the surface concentration of the oxidant at each of the nodes in the present time step. Then, the first value of the surface concentration of the oxidant at each of the nodes in the SiO2 region is adjusted to generate the second value of the surface concentration of the oxidant at each of the nodes in the SiO2 region in the present time step. Also, the second value of the surface concentration of the oxidant in the present time step is set as zero with respect to one of the nodes where the thickness increase of the SiO2 region has a value equal to or less than the specific small value. Simultaneously with this, the first value of the surface concentration of the oxidant is stored for a next time step.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: September 4, 2001
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 6044213
    Abstract: The present invention provides a method of simulating a process for oxidation of silicon. The method comprises the following steps. A time "t" of oxidation calculation is set at zero. An effective surface oxidant concentration of a silicon surface exposed to an oxygen atmosphere is calculated assuming that a spontaneous silicon oxide film as an initial silicon oxide film extends over the silicon surface. The time "t" of oxidation calculation is forwarded by a predetermined time increment .DELTA.t. An oxidation rate is calculated by use of one of the effective surface oxidant concentration and the surface oxidant concentration. A new silicon surface is formed based upon the calculated oxidation rate and the time increment .DELTA.t. Variations in thickness of the silicon oxide film over time are found by a deformation calculation.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: March 28, 2000
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 6041174
    Abstract: A process simulator for an oxidation enhanced diffusion formulates an enhanced velocity of diffusion coefficient into a partial differential equation expressed as (div grad F.sub.OED =F.sub.OED), and solves the partial differential equation through a conversion of discrete representation under the boundary conditions containing an oxidizing velocity at the boundary between a silicon layer and a silicon oxide layer so that the program sequence becomes simple.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: March 21, 2000
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 6011914
    Abstract: A method for simulating the deformation of regions in a semiconductor device due to oxidation. An oxidation calculation triangular mesh is deformed according to an oxidation calculation, and a diffusion calculation triangular mesh simulates the diffusion of impurity materials. Diffusion calculation control volumes are defined to each vertex of the diffusion calculation triangular mesh. The diffusion calculation triangular mesh and the diffusion calculation control volumes are deformed according to the deformation of the oxidation calculation triangular mesh. Impurity material concentrations are altered according to volume ratio of the diffusion calculation control volume after deformation to the diffusion calculation control volume before deformation. A new diffusion calculation triangular mesh and corresponding new diffusion calculation control volumes are defined for deformed shapes of regions that guarantee Delaunay partitioning.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: January 4, 2000
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 5930494
    Abstract: A process simulator comprising a triangular mesh generating unit for generating a triangular mesh to a semiconductor device to be processed, a control volume defining unit for defining a control volume on the triangular mesh, an impurity concentration setting unit for setting up the concentration of impurity with respect to the control volume, an oxidation calculating unit for calculating an oxidation process and deforming the triangular mesh, a control volume deforming unit for deforming the control volume, an impurity concentration modifying unit for modifying the impurity concentration according to the deformed control volume, an impurity concentration transferring unit for transferring the modified impurity concentration to the control volume defined on the triangular mesh newly generated to the deformed semiconductor device, and a diffusion calculating unit for performing a diffusion calculation.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: July 27, 1999
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 5798764
    Abstract: A method is described for determining an intersection of a boundary of a body with each of Delaunay partitioned tetrahedra, the body exhibiting edges and faces. Firstly, a plurality of first tetrahedra are produced by dividing the body into a plurality of triangular prisms and then dividing each triangular prism into a plurality of tetrahedra, which is a face segment of said body, is found. Further, any edge of each first tetrahedron, which is an edge segment of said body is found. Subsequently, a plurality of second tetrahedra are generated each of which is Delaunay partitioned. Thereafter, the following steps are cyclically implemented to investigate in sequence all of the second tetrahedra. A unique point within the second tetrahedron is determined and then, a third tetrahedron which includes the unique point therewithin is determined among the first tetrahedra.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: August 25, 1998
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 5774696
    Abstract: A method for eliminating intersections between a substance boundary and triangles (or tetrahedra) of a triangle mesh (or tetrahedron mesh) which satisfies a condition of Delaunay partition and is used for a finite difference method. First, triangles intersecting with the substance boundary are searched out. One of the vertices of any of the triangles is selected as a moving node P and the moving node is projected to the substance boundary to obtain a projected point P'. Processing object triangles which commonly have the moving node and peripheral triangles which are positioned around the processing object triangles are listed. Then, checking to detect whether or not the projected point is included in a circumscribed circle about any of the peripheral triangles is performed. When the projected point is included in a circumscribed circle, a node is added at the projected point and triangles are produced using the node.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: June 30, 1998
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 5675522
    Abstract: In order to divide an analyzing region in a semiconductor device into a plurality of fractional elements of a predetermined configuration, the analyzing region is initially divided into an arbitrary number of the fractional elements. With respect to a newly added nodal point, the fractional elements enclosing the new nodal point within a circumscribing range thereof are extracted as objective fractional elements for further division. Among the extracted fractional elements, specific fractional element having the perimetric fraction located within a predetermined modifying the perimeter of the fractional element group consisted of the extracted fractional elements. The fractional elements are re-establishes on the basis of the modified perimeter and the new nodal point.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: October 7, 1997
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 5671395
    Abstract: A region of a semiconductor device to be analyzed is initially divided a plurality of fractional elements of predetermined configuration. With respect to each fractional element, adjacent element information is provided. Then, a new nodal point is added. Then, one fractional element having a circumscribed circle enclosing the new nodal point is retrieved. Another fractional elements adjacent the retrieved fractional element and having the circumscribed circle enclosing the new nodal point are retrieved for establishing a fractional element group of the fractional elements having the circumscribed circles enclosing the new nodal point. The fractional elements are established on the basis of the boundary of the fractional element group and the new nodal point. The adjacent element information is then added for respective of the newly established fractional elements.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: September 23, 1997
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama
  • Patent number: 5289384
    Abstract: It is an object of this invention to make it possible to accurately simulate a manner in which carriers are transferred in a semiconductor device. A Fermi level setting means sets a Fermi level in a sink region of carriers, such as a vertical CCD portion of a CCD, and Boltzmann distribution equation solving means solve a Boltzmann distribution equation to obtain a carrier density in this Fermi level set region. In a CCD, the manner in which carriers are transferred from a photodiode portion to a vertical CCD portion in a CCD can be simulated accurately.
    Type: Grant
    Filed: January 23, 1992
    Date of Patent: February 22, 1994
    Assignee: NEC Corporation
    Inventor: Yutaka Akiyama