Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

Abstract: The exposure apparatus comprises a gas supply system that supplies a low absorptive gas with a predetermined purity to the illumination system housing and the barrel of the projection optical system and collects the gas exhausted from these closed spaces and supplies the gas to the mask chamber which houses the mask stage and the substrate chamber which houses the substrate stage. The illumination system housing, the barrel of the projection optical system, the mask chamber, and the substrate chamber are respectively located on the optical path of the exposure light. Accordingly, the low absorptive gas that has circulated the illumination system housing and the barrel of the projection optical system is used as the replacement gas of the mask chamber and the substrate chamber, while sufficiently satisfying the purity of the low absorptive gas and maintaining the transmittance of the exposure light required in each chamber.

Abstract: A vibration isolation apparatus for preventing shaking and vibration of a stage of an exposure apparatus or the like uses a vibration isolation mount formed of a spring buffer system employing a spring member and a fluid buffer system employing a viscous fluid as a vibration isolation base which is disposed between a base member on which an exposure unit is mounted and an installation surface on which the base member is installed so as to support the base member. The coefficient of viscous drag of the viscous fluid is varied to vary a damping coefficient which depends on the coefficient of viscous drag thereby to vary rigidity of the vibration isolation mount, whereby vibration transmitted from an external source and vibration associated with a stage movement are damped.

Abstract: An electronic device has a frame and a back board having plural logical units and power supply units mounted thereon. The logical units and the power supply units are alternately located on both sides of the back board in the center of the frame so that the power supply units mounted on one side of the back board may feed a power to the closest logical units mounted on the other side. Further, the air flow paths to be circulated through the logical units and the power supply units are formed so that each unit may be efficiently cooled by the air fed by an air fan unit. As a result, the feeding voltage becomes uniform and the cooling efficiency is improved.

Abstract: A semiconductor memory cell comprising a first transistor of a first conductivity type for read-out, a second transistor of a second conductivity type for write-in and a junction-field-effect transistor of the first conductivity type for current control; the first transistor having source/drain regions constituted of a first region and a fourth region, and a channel forming region constituted of a surface region of a third region; the second transistor having source/drain regions constituted of a second region and the third region, and a channel forming region constituted of a surface region of the first region; the junction-field-effect transistor having gate regions constituted of the fifth region and a portion of the third region facing the fifth region, a channel region constituted of part of the fourth region sandwiched by the fifth region and said portion of the third region, and source/drain regions constituted of the fourth region.

Abstract: A movable mirror supporting mechanism for supporting a movable mirror forming a part of an interferometric measurement system and having a rectangular cross-section onto an object, with a reflecting surface of said movable mirror being arranged normal to a measuring direction. The movable mirror supporting mechanism includes at least two fixtures for securing the movable mirror from above onto respective movable mirror supporting portions provided on the object. Positions on the movable mirror at which the movable mirror is secured onto the measuring object by the fixtures are defined to be out of that area of the reflecting surface of the movable mirror which is utilized for interferometric measurement.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: The present invention provides a structure for isolating the reaction forces generated by a planar motor. Specifically, the fixed portion of the reaction motor, which is subject to reaction forces, is structurally isolated from the rest of the system in which the planar motor is deployed. In accordance with one embodiment of the present invention, the fixed portion of the planar motor is separated from the rest of the system and coupled to ground. The rest of the system is isolated from ground by deploying vibration isolation means. Alternatively or in addition, the fixed portion of the planar motor may be structured to move (e.g., on bearings) in the presence of reaction forces, so as to absorb the reaction forces with its inertia. In a further embodiment of the present invention, the fixed portion of the planar motor and the article to be moved are supported by the same frame, with the fixed portion of the planar motor movable on bearings.

Abstract: Provided is a semiconductor memory cell which requires no refreshing operation for retaining information. The semiconductor memory cell comprises a first transistor TR1 having a first conductivity type, a second transistor TR2 having a second conductivity type and a MIS type diode DT for retaining information, wherein one source/drain region of the first transistor TR1 corresponds to the channel forming region CH2 of the second transistor TR2, one source/drain region of the second transistor TR2 corresponds to the channel forming region CH1 of the first transistor TR1, one end of the MIS type diode DT is formed of an extending portion of the channel forming region CH1 of the first transistor TR1, and the other end of the MIS type diode DT is constituted of an electrode which is formed of an electrically conductive material and connected to a third line having a predetermined potential.

Abstract: A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a MONOS control gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a sidewall MONOS control gate with an ultra short channel under the control gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Abstract: A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, and (E) a non-linear resistance element having at least two ends with one end connected to the first gate.

Abstract: A semiconductor memory cell includes a read-out transistor of a first conductivity type which has source/drain regions constituted by a second conductive region and a third semiconducting region, a channel forming region constituted by a surface region of a second semiconducting region, and a conductive gate formed on a barrier layer; a switching transistor of a second conductivity type which has source/drain regions constituted by a first conductive region and the second semiconducting region, a channel forming region constituted by a surface region of a first semiconducting region, and a conductive gate formed on a barrier layer; and a current controlling junction-field-effect transistor of a first conductivity type which has gate regions constituted by a third conductive region and a portion of the second semiconducting region, a channel region constituted by a portion of the third semiconducting region, and one source/drain region extended from one end of the channel region, being constituted by a portion

Abstract: A non-volatile memory device in which gate electrodes are formed on an upper surface and a lower surface of the channel via insulating layers, respectively, one of them is used as a read electrode and the other is used as a write electrode, whereby, at a read operation, the reading is carried out with a reduced influence upon stored charges stored at the time of writing. Particularly, it has a structure in which a source and drain region of the non-volatile semiconductor memory device is formed in the semiconductor layer formed on the insulating layer and, at the same time, one of the read electrode and write electrode is buried in the insulating layer.

Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Abstract: A method of fabricating a light valve device comprises forming a substrate having stacked layers including a light-shielding thin film layer, an insulating film, and a single crystalline semiconductor thin film stacked in this order on a transparent support substrate. A light-shielding layer pattern is formed by selectively etching the stacked layers. Thereafter, a switching element is formed comprised of a transistor having a channel region formed in the single crystalline semiconductor thin film and a main gate electrode covering the channel region. The channel region is provided over the light-shielding pattern layer to prevent light incident from the transparent support substrate from illuminating the channel region to suppress a photo-induced leakage current in the channel region. A transparent electrode is formed and is electrically connected to the switching element.

Abstract: A vibration isolation mount is provided for supporting an apparatus with respect to an installation surface and for controlling vibration of the apparatus. The vibration isolation mount includes a support mount having a first end connected to the installation surface and a second end fixed to the apparatus to support the apparatus with respect to the installation surface, wherein the support mount receives a force from the apparatus along a first line of action; and an actuator adjacent the support mount, the actuator having a first end connected to the installation surface and a second end in contact with the apparatus, the actuator being movable to exert a controlling force for controlling the vibration to the apparatus along a second line of action coincident with the first line of action.

Abstract: A movable mirror supporting mechanism for supporting a movable mirror forming a part of an interferometric measurement system and having a rectangular cross-section onto an object, with a reflecting surface of said movable mirror being arranged normal to a measuring direction. The movable mirror supporting mechanism includes at least two fixtures for securing the movable mirror from above onto respective movable mirror supporting portions provided on the object. Positions on the movable mirror at which the movable mirror is secured onto the measuring object by the fixtures are defined to be out of that area of the reflecting surface of the movable mirror which is utilized for interferometric measurement.

Abstract: The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises a composite substrate having a supporte substrate, a light-shielding thin film formed on said supporte substrate and semiconductive thin film disposed on the light-shielding thin film with interposing an insulating thin film. A switching element made of a transistor and a transparent electrode for driving light valve are formed on the semiconductive thin film, and the switching element and the transparent electrode are connected electrically with each other. The transistor includes a channel region in the semiconductive thin film and a main gate electrode for controlling the conduction in the channel region, and the light-shielding thin film layer is so formed as to cover the channel region on the side opposite to said channel region, so as to prevent effectively a back channel and shut off the incident light.