Patents by Inventor Yutaka Hoshino

Yutaka Hoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8962418
    Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Hoshino
  • Patent number: 8842955
    Abstract: An optical fiber cable enabling further reduction of possibilities of disconnection of optical fiber due to, for instance, cicada oviposition. The optical fiber cable (10) is provided with: an optical fiber core (1); a tension member (2), which is arranged in parallel to the optical fiber core (1) on one side or on the both sides of the optical fiber core (1); and a sheath (3) which integrally covers the optical fiber core (1) and the tension member (2). At least one portion of the sheath (3) is composed of a polymeric material having a yield point stress of 12 MPa or higher.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: September 23, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Masayoshi Tsukamoto, Yutaka Hoshino, Noboru Okada
  • Patent number: 8837886
    Abstract: An optical fiber cable which is suitably set in a conduit by pushing the optical fiber cable into the conduit so as to insert the optical fiber cable through the conduit and which does not reduce the ease of manufacture and the mechanical characteristics of the optical fiber cable. The optical fiber cable includes an optical fiber cable core wire and a sheath covering the optical fiber cable core wire, wherein a dynamic friction coefficient between a surface of the sheath of the optical fiber cable and a surface of a sheath of another optical fiber cable is 0.17 to 0.34, and a dynamic friction coefficient between the surface of the sheath of the optical fiber cable and a surface of a sheet composed of polyvinyl chloride is 0.30 to 0.40.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: September 16, 2014
    Assignees: Furukawa Electric Co., Ltd., Nippon Telegraph and Telephone Corporation
    Inventors: Yutaka Hoshino, Masayoshi Tsukamoto, Koichi Mizuno, Eiji Konda, Keiichiro Sugimoto, Shinichi Niwa
  • Publication number: 20140206155
    Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Komaki INOUE, Yutaka HOSHINO
  • Patent number: 8779855
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Akihiko Furukawa, Satoshi Yamakawa, Tsuyoshi Kawakami, Masao Kondo, Yutaka Hoshino
  • Publication number: 20130265109
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Application
    Filed: May 29, 2013
    Publication date: October 10, 2013
    Inventors: Tetsuya IIDA, Akihiko FURUKAWA, Satoshi YAMAKAWA, Tsuyoshi KAWAKAMI, Masao KONDO, Yutaka HOSHINO
  • Patent number: 8482058
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Patent number: 8461927
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa, Tetsuya Iida, Masao Kondo, Yutaka Hoshino
  • Patent number: 8344454
    Abstract: An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kyoya Nitta, Yutaka Hoshino
  • Patent number: 8330544
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa, Tetsuya Iida, Masao Kondo, Yutaka Hoshino
  • Publication number: 20120235250
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Application
    Filed: June 1, 2012
    Publication date: September 20, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20120228711
    Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region . It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer , step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region , step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 13, 2012
    Inventor: Yutaka HOSHINO
  • Patent number: 8232595
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Publication number: 20120133431
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Tsuyoshi KAWAKAMI, Akihiko FURUKAWA, Satoshi YAMAKAWA, Tetsuya IIDA, Masao KONDO, Yutaka HOSHINO
  • Patent number: 8134408
    Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Kawakami, Akihiko Furukawa, Satoshi Yamakawa, Tetsuya Iida, Masao Kondo, Yutaka Hoshino
  • Patent number: 8129784
    Abstract: The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n+-type source region of an LDMOSFET, and no such metal silicide film is formed on an n?-type offset drain region, an n-type offset drain region, and an n+-type drain region. A side wall spacer comprising a silicon film is formed via an insulating film on the side wall of the gate electrode over the drain side thereof, and a field plate electrode is formed by this side wall spacer. The field plate electrode does not extend above the gate electrode, and a metal silicide film is formed over the entire upper surface of the gate electrode in the silicide process.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Hatori, Yutaka Hoshino
  • Patent number: 8080831
    Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: December 20, 2011
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Fumitaka Nakayama, Masatoshi Morikawa, Yutaka Hoshino, Tetsuo Uchiyama
  • Publication number: 20110278581
    Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 17, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Komaki INOUE, Yutaka HOSHINO
  • Publication number: 20110254087
    Abstract: To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n? type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Inventors: Tomoyuki MIYAKE, Masatoshi Morikawa, Yutaka Hoshino, Makoto Hatori
  • Publication number: 20110255834
    Abstract: An optical fiber cable enabling further reduction of possibilities of disconnection of optical fiber due to, for instance, cicada oviposition. The optical fiber cable (10) is provided with: an optical fiber core (1); a tension member (2), which is arranged in parallel to the optical fiber core (1) on one side or on the both sides of the optical fiber core (1); and a sheath (3) which integrally covers the optical fiber core (1) and the tension member (2). At least one portion of the sheath (3) is composed of a polymeric material having a yield point stress of 12 MPa or higher.
    Type: Application
    Filed: December 24, 2009
    Publication date: October 20, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masayoshi Tsukamoto, Yutaka Hoshino, Noboru Okada