Abstract: A method of coding a signal for digital optical communication using a symbol formed of N slots [s1, s2, s3, . . . sN], wherein si is either 0 or 1 where i is an integer and l≦i ≦N is provided. The method includes the steps of determining a plurality of symbols which satisfy the following expression, wherein k is an arbitrary positive integer, and p1, q1, p2, q2, . . . , pk and qk are integers which satisfy 1≦p1<q1, 1≦p2<q2, . . . , 1≦pk<qk, and p1/q1<p2/q2<. . .

Abstract: A DLL circuit includes a counter control circuit. The counter control circuit includes an inverter, a NAND gate, a shift register, a clocked inverter, and a NOR gate. When a reset signal RST of an H level, or a smallest address signal CMIN indicating the smallest value of the address is input, the counter control circuit forces a signal REV to be switched to an H level and generates a counter control signal ADD and a signal EN of an H level, whereby the counter enters a force up mode. As a result, the delay clock CLKD can be set in phase with a reference clock CLK stably.

Abstract: A digital optical transmitter includes a main/subdata modulation part for distorting a main data modulated signal waveform in response to sub-data, and an E/O conversion part for converting a subsequently obtained electrical modulated signal to an optical modulated signal and outputting the optical modulated signal. A digital optical receiver includes an O/E conversion part for receiving the optical modulated signal, converting it to an electrical modulated signal, and outputting the electrical modulated signal. Additionally, the digital optical receiver further includes a main/subdata demodulation part for demodulating the main data from the electrical modulated signal, while detecting whether or not a distortion signal responsive to the subdata is superposed on a subcarrier which forms the electrical modulated signal. If the distortion signal is superposed on a subcarrier, the main/subdata demodulator part demodulates the associated subdata.

Abstract: A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output terminal of the second inverter and the first and second inverters are configured of inverters of different sizes. A phase comparator compares a delay clock's phase with a reference clock's phase and a result of the phase comparison is referred to to count addresses which are in turn used to selectively drive the inverters configuring the first and second inverter circuits, to allow the fine delay circuit to output a signal having a phase between signals having therebetween a phase difference of a fixed amount. Thus the clock's phase can be adjusted with high precision.

Abstract: An output circuit is driven by a first differential amplification circuit having an N-channel differential amplification stage that compares a reference voltage VREF with an input signal IN, and a second differential amplification circuit having a P-channel differential stage. An output of the first differential amplification circuit is given as the gate voltage of P-channel MOS transistors in the output circuit, and an output of the second differential amplification circuit is given as the gate voltage of N-channel MOS transistors in the output circuit. This realizes an input buffer with reduced error operations even under threshold voltage variations caused by process variations and others.

Abstract: Consuming current must be reduced in each operation state of a semiconductor device which operates in synchronized with an external clock signal. However, in each operation state, for satisfying the stability of an operation and a speedup, the suppression of consuming current has been performed under difficult circumstances. For solving this problem, a clock generation circuit generating an internal clock signal based on an external clock signal is activated during a specific time period when a clock synchronization circuit is in a state of inactivation.

Abstract: An output circuit is driven by means of a first differential amplification circuit having an N-channel differential amplification stage that compares a reference voltage VREF with an input signal IN, and a second differential amplification circuit having a P-channel differential stage. An output of the first differential amplification circuit is given as the gate voltage of P-channel MOS transistors in the output circuit, and an output of the second differential amplification circuit is given as the gate voltage of N-channel MOS transistors in the output circuit. This realizes an input buffer with reduced error operations even under threshold voltage variations caused by process variations and others.

Abstract: A DLL circuit includes a counter control circuit. The counter control circuit includes an inverter, a NAND gate, a shift register, a clocked inverter, and a NOR gate. When a reset signal RST of an H level, or a smallest address signal CMIN indicating the smallest value of the address is input, the counter control circuit forces a signal REV to be switched to an H level and generates a counter control signal ADD and a signal EN of an H level, whereby the counter enters a force up mode. As a result, the delay clock CLKD can be set in phase with a reference clock CLK stably.

Abstract: A DLL circuit includes a fine delay circuit including a first inverter circuit, a second inverter circuit and delay units. The first inverter circuit has an output terminal connected to an output terminal of the second inverter and the first and second inverters are configured of inverters of different sizes. A phase comparator compares a delay clock's phase with a reference clock's phase and a result of the phase comparison is referred to to count addresses which are in turn used to selectively drive the inverters configuring the first and second inverter circuits, to allow the fine delay circuit to output a signal having a phase between signals having therebetween a phase difference of a fixed amount. Thus the clock's phase can be adjusted with high precision.

Abstract: In accordance with the present invention a semiconductor memory device includes a connection control circuit controlling a connection between a bit line pair and a data input/output line pair. The connection control circuit includes a flip flop. The connection control circuit responds to a sense amplifier activation signal and a column bank address by setting a level of an interlock signal controlling a gate for electrically connecting the bit line pair and the data input/output line pair together.

Abstract: A row predecoder receives internal address signals output from address latch circuits and outputs the predecode signals. A spare determination circuit receives address signals and outputs a comparison result with a defective row address stored in advance. A normal row decoder receives a predecode address signal and selects a word line within a corresponding normal memory cell block when a redundancy replacement is not performed, while a redundant row decoder receives a predecode signal and selects a redundant word line within a redundant memory cell block when the redundancy replacement is performed.

Abstract: A method of coding a signal for digital optical communication using a symbol formed of N slots [s1, s2, s3, . . . sN], wherein si is either 0 or 1 where i is an integer and l≦i<≦N is provided. The method includes the steps of determining a plurality of symbols which satisfy the following expression, wherein k is an arbitrary positive integer, and p1, q1, p2, q2, . . . , pk and qk are integers which satisfy 1≦p1<q1, 1≦p2<q2, . . . , 1≦pk<qk, and p1/q1<p2/q2<. . .

Abstract: Only one sense signal line for driving a sense amplifier is arranged in each sense amplifier band. Each sub-array is provided with a sub-sense signal generator for generating two sub-sense signals in response to a main sense signal sent from one main sense signal line. The sub-sense signal is applied to the plurality of sense amplifiers corresponding to each sub-array. Since only one main sense signal line is arranged in each sense amplifier, a layout area is reduced. Preferably, a transistor of a first inverter in the sub-sense signal generator is smaller in size than a transistor of a final inverter. Thereby, a significant delay of the sub-sense signal does not occur in a position remote from a source of the main sense signal.

Abstract: A method of coding a signal for digital optical communication using a symbol formed of N slots [s1, s2, s3, . . . , sN], wherein si is either 0 or 1 where i is an integer and 1≦i≦N is provided. The method includes the steps of determining a plurality of symbols which satisfy the following expression, wherein k is an arbitrary positive integer, and p1, q1, p2, q2, . . . , pk and qk are integers which satisfy 1≦p1<q1, 1≦p2<q2, . . . , 1≦pk<qk, and p1/q1<p2/q2< . . .

Abstract: In a circuit producing a reference voltage that is used in an internal circuit having an operation mode switched by utilizing a MOS transistor receiving a constant voltage on its gate, a signal changing in a direction controlling a voltage change caused on a gate node is applied to the gate or a drain of the MOS transistor receiving the constant voltage on the gate when the operation mode is switched. The constant voltage can be suppressed from varying through capacitive coupling of a parasitic capacitance of the constant voltage MOS transistor when the operation mode is switched, so that the reference voltage can be stably produced.

Abstract: A semiconductor integrated circuit device includes an internal voltage-down converter and a voltage compensation circuit. The internal voltage-down converter provides an internal power supply voltage. The voltage compensation circuit includes a comparator, a capacitor, a transistor, and a constant current source. When the voltage (internal power supply voltage) of the output node suddenly drops, the potential at the positive input of the comparator is reduced by the coupling effect of the capacitor. As a result, the output node is charged. The potential of the positive input of the comparator is charged. As a result, the charging with respect to the output node ends.

Abstract: A semiconductor memory device includes an output control signal generation circuit for generating an output control signal to designate initiation of data output according to an external control signal, and a boosting circuit boosting an external power supply voltage. Each of the plurality of output control circuits generates an output permit signal with the output level of the boosting circuit as the activation level in response to activation of an output control signal. The output permit signals are transmitted to a plurality of output circuits by a corresponding one of a plurality of signal lines. Each of the plurality of output circuits drives the potential of a corresponding output terminal according to a read out data signal and an output permit signal.

Abstract: An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.

Abstract: A PTC thermistor element for a heating device has a main body of a layered structure having a thinner layer and a thicker layer, sandwiched between electrodes formed on the main outer surfaces facing away from each other. The thinner layer has a thickness 0.05-0.43 times that of the thicker layer and is made of a PTC thermistor material with a Curie temperature which is lower than that of the thicker layer by 20.degree. C. or more. The center of heat generation is thus shifted towards the electrode formed on the thinner layer, and a heating plate contacting it can be effectively heated.

Abstract: A row address signal output from an internal row address generation circuit according to an output from a ring oscillator activated in response to an externally applied burn-in mode designation signal SBT, is scrambled by an operation circuit and then applied to a row decoder. Meanwhile, a signal output from a data output circuit in response to activation of signal SBT is scrambled by a data scrambler and checker pattern data is applied to a memory cell array such that it corresponds to a physical address of the memory cell array.