Abstract: A surface mountable electronic device has a case with an opening, an electronic element contained inside the case such as a thermistor or a varistor that generates heats when in operation, a plurality of elongated spring terminals supporting this electronic element elastically together and each sandwiching a wall of the case both from inside and outside at a peripheral edge part of the wall at its opening, and a lid attached to the case so as to close up its opening except where the spring terminals pass through the opening. Grooves are preferably formed at peripheral edge parts of the wall where the spring terminals are fitted, contacting the wall such that heat generated by the electronic element during its operation and propagating through the spring terminals can be effectively conducted to the main body of the case and diverted from its soldered junctures with a circuit board.

Abstract: A photoconductor for internal irradiation electrophotography includes a substrate which is hollow, cylindrical, and transparent, and which is composed of a synthetic resin; an electroconductive layer which is provided on an outer surface of the substrate and which has a surface resistance of no higher than 2.times.10.sup.6 .OMEGA./square; a photosensitive layer which is composed of organic material, which is provided on the electroconductive layer, and which is dip coated from a liquid including an organic solvent; and a protective layer which is provided on an inner surface of the substrate, wherein the protective layer and the electroconductive layer are resistant to the organic solvent of the liquid for dip coating.

Abstract: A demagnetizing circuit and a current limiting device for being built into a power supply circuit of a color television receiver or color monitor display or the like with which it is possible to effect a reliable demagnetizing operation using existing components and without using either a positive characteristic thermistor which reaches a high temperature or a relay circuit. The demagnetizing circuit is connected in parallel with a power supply circuit having a smoothing capacitor and a negative temperature characteristic thermistor or fixed resistance for suppressing surge currents to the smoothing capacitor. It has a thermally actuated switch connected in series with one end of a demagnetizing coil by way of a positive temperature characteristic thermistor which is actuated by heat produced by the temperature negative characteristic thermistor or fixed resistance to cut off a demagnetizing current.

Abstract: In a DRAM, first and second P channel MOS transistors are connected in series between an output node of an NOR gate of an input buffer and a power supply line. The first P channel MOS transistor receives at its gate an external signal /EXT and the second P channel MOS transistor receives at its gate an inverted signal of an output enable signal OEM. In a data output period, the signal OEM attains to the "H" level and the second P channel MOS transistor is rendered conductive, and therefore, even when power supply potential Vcc lowers in the data output period, the output node can be sufficiently charged, and an internal signal /INT can be generated stably.

Abstract: A demagnetizing circuit has a positive characteristic thermistor and a demagnetizing coil connected in series with an alternating current power supply and is so constructed that it is possible to suppress the production of a low-frequency electromagnetic field. After the completion of a demagnetizing operation, the demagnetizing coil and the alternating current power supply can be completely isolated from each other, i.e. both ends of the demagnetizing coil can be electrically cut off from the alternating current power supply, so that it is impossible for residual demagnetizing current from the alternating current power supply to produce a low-frequency electromagnetic field in the demagnetizing coil. Also, preferably, at least one end of the demagnetizing coil is kept at a reference potential by way of a capacitor to dissipate any currents which may be induced in the demagnetizing coil by any influence other than the alternating current power supply.

Abstract: A component for a demagnetization circuit includes a thermistor with positive temperature characteristic having a first electrode and a second electrode, another thermistor with negative temperature characteristic having a third electrode and a fourth electrode and being disposed such that the first and third electrodes are opposite to each other, a heat-sensitive switch disposed between these two thermistors, a case which contains the thermistors and a heat-sensitive switch, and terminals which extend outward from inside the case.

Abstract: In one example of a demagnetization (degaussing) circuit, main electrodes of a TRIAC, a first positive temperature characteristic thermistor and a demagnetization coil are connected in series to both ends of an AC supply, and a heat-sensitive switch and a heating resistor are connected in series between an end of the TRIAC on the side of the AC supply and an end of the demagnetization coil on the side of the AC supply. A connecting point between the heat-sensitive switch and the heating resistor is connected to a gate electrode of the TRIAC, and the heat-sensitive switch and the heating resistor are thermally coupled to each other. The disclosed demagnetization circuit does not need a secondary electric circuit such as a relay control circuit and allows easy substrate design, with a small number of components and at low cost.

Abstract: An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage while not increasing layout area. A differential amplifying circuit in a voltage down converter controls potential level V.sub.OUT of the drain of transistor P14 such that it attains the reference potential V.sub.REF. If the potential V.sub.OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V.sub.OUT is pulled down. By contrast, if the potential level V.sub.OUT lowers, transistor P12 is rendered conductive, and the potential level V.sub.OUT is pulled up.

Abstract: A demagnetization circuit controls a demagnetization current to its demagnetization coil by means of a PTC thermistor with positive characteristic. The PTC thermistor is connected in series with and thermally coupled to a heat-sensitive switch. An NTC thermistor with negative characteristic for suppressing rush current of the voltage source is also thermally coupled to the heat-sensitive switch. After a power switch is closed, the heat-sensitive switch is opened by the heat emitted from the PTC thermistor and remains open by the heat from the NTC thermistor. The two thermistors and the heat-sensitive switch are contained in a case for easy handling and to make the component compact.

Abstract: A semiconductor integrated circuit comprises a NAND gate which constitutes a previous stage circuit, a reset circuit, a charging circuit, and a capacitor for generating a boost potential. A signal of a node A expressing data and a signal of a node B expressing permission of outputting data are not only input to the NAND gate, but also to the reset circuit, and the output of the reset circuit is not only input to the charging circuit but also to the NAND gate; therefore, the previous stage circuit and the reset circuit are interlinked with the output signals. In the result, even in a case where noise is generated in the node A, it is possible to obtain a sufficient boost potential generated in the capacitor.

Abstract: An improved DRAM is disclosed, in which a number of sense amplifiers to be activated simultaneously can be selected by using a bonding option method. An output signal /.o slashed..sub.A supplied from a bonding option circuit 11 is applied to column interlock releasing circuit 7. When an operation mode in which the number of the sense amplifiers to be activated simultaneously is large is selected, a column interlock releasing signal /.o slashed. is delayed, and enabling of a column decoder 3 is delayed. In the operation mode, in which the number of the sense amplifiers to be activated simultaneously is large, the enabling of the column decoder 3 is delayed, and a conducting timing of an IO gate circuit 16 is delayed. A sense amplifier 15 can sufficiently amplify a potential difference between bit lines, so that an error in the data reading operation is prevented.

Abstract: A memory array block MK of the same structure is arranged in all the memory array regions MA of a DRAM. An IO line control circuit connects the other end of a pair of local signal input/output lines to one end of a pair of global signal input/output lines in an opposite phase or a positive phase in response to one end of the corresponding pair of local signal input/output lines being connected to an even numbered bit line pair of the upper row of memory array region MA or an odd numbered bit line pair of the lower row of memory array region MA. Since the memory array blocks MK in all the memory array region MA have the same structure, a memory cell corresponding to a defective address detected in a BI test can easily be identified.

Abstract: An improved DRAM is disclosed, in which a number of sense amplifiers to be activated simultaneously can be selected by using a bonding option method. An output signal /.phi..sub.A supplied from a bonding option circuit 11 is applied to column interlock releasing circuit 7. When an operation mode in which the number of the sense amplifiers to be activated simultaneously is large is selected, a column interlock releasing signal /.phi. is delayed, and enabling of a column decoder 3 is delayed. In the operation mode, in which the number of the sense amplifiers to be activated simultaneously is large, the enabling of the column decoder 3 is delayed, and a conducting timing of an IO gate circuit 16 is delayed. A sense amplifier 15 can sufficiently amplify a potential difference between bit lines, so that an error in the data reading operation is prevented.

Abstract: A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Abstract: Disclosed is a semiconductor memory device having such a structure that a voltage variation on a bit line does not affect a voltage on another bit line. A gate electrode portion branches and extends laterally from a word line and extends almost in parallel with the bit line. First and second impurity regions of a field effect transistor are formed in regions between adjacent word lines, with the gate electrode portion therebetween. A capacitor electrically connected to the second impurity region is formed to cover the bit lines. Since the capacitor is between adjacent bit lines, no voltage variation on one bit line affects a voltage on the other bit lines.

Abstract: An upper column address strobe signal and a lower column address strobe signal applied to a dynamic RAM are 180.degree. out of phase from each other. Data of n bits are read out from a memory cell array at a time. The data read out from memory cell array is divided into two bit groups and applied to an upper IO buffer and a lower IO buffer. Upper IO buffer and lower IO buffer latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus in response to the upper column address strobe signal and the lower column address strobe signal.

Abstract: An improved output buffer circuit applicable to dynamic random access memories (DRAms) is disclosed. First power supply voltage Vcc1 is supplied to a conventional output main amplifier 3ai. Second power supply voltage Vcc2 is supplied to output driver circuit 4i. Potential fixing circuit 3bi operated in response to power supply failure detecting signal PFR of first power supply voltage Vcc1 is connected to the output of output main amplifier circuit 3ai. When second power supply voltage Vcc2 is applied without first power supply voltage Vcc1 being supplied, the gates of driving transistors Q1 and Q2 are fixed to ground potential in response to the signal PFR. Consequently, undesired current consumption is avoided, since a penetrating current does not flow through transistors Q1 and Q2.

Abstract: An output circuit for providing data read from a memory cell is disclosed. When a power source is turned on, initial value data set in a register circuit is read and then latched in comparison circuits. The data latched in the comparison circuits are applied through NOR circuits to a plurality of transistors, so that the transistors corresponding in number to the initial value data are rendered conductive. An output signal is fed back from a common output terminal of the respective transistors to the comparison circuits, so that the respective comparison circuits compare between respective threshold values and the output signal. Thus, a determination is made as to whether the gradient of leading edges of waveforms of the output signal is sharp or gradual. If the gradient is gradual, the number of transistors becoming conductive increases, whereas if the gradient is sharp, the number of such transistors decreases.

Abstract: Disclosed is a semiconductor memory device having such a structure that a voltage variation on a bit line does not affect a voltage on another bit line. A gate electrode portion branches and extends laterally from a word line and extends almost in parallel with the bit line. First and second impurity regions of a field effect transistor are formed on regions between adjacent word lines, with the gate electrode portion therebetween. A capacitor electrically connected to the second impurity region is formed to cover the bit lines. Since the capacitor is between adjacent bit lines, no voltage variation on one bit line affects a voltage on the other bit lines.