Patents by Inventor Yutaka Okazaki
Yutaka Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10944014Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.Type: GrantFiled: July 17, 2019Date of Patent: March 9, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
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Publication number: 20210057587Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: ApplicationFiled: August 31, 2020Publication date: February 25, 2021Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
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Patent number: 10763373Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: GrantFiled: March 28, 2019Date of Patent: September 1, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
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Publication number: 20200258914Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Tomoaki MORIWAKA, Shinya SASAGAWA, Takashi OHTSUKI
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Patent number: 10734487Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator over a substrate, an oxide over the first insulator, a second insulator over the oxide, a conductor overlapping with the oxide with the second insulator therebetween, a third insulator in contact with a top surface of the oxide, a fourth insulator in contact with a top surface of the third insulator, a side surface of the second insulator, and a side surface of the conductor, and a fifth insulator in contact with a side surface of the fourth insulator, a side surface of the third insulator, and the top surface of the oxide. The third insulator has a lower oxygen permeability than the fourth insulator.Type: GrantFiled: January 15, 2019Date of Patent: August 4, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki Komagata, Naoki Okuno, Yutaka Okazaki, Hiroshi Fujiki
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Publication number: 20200220028Abstract: A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length.Type: ApplicationFiled: March 17, 2020Publication date: July 9, 2020Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Yutaka OKAZAKI
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Patent number: 10685983Abstract: To provide a semiconductor device capable of retaining data for a long time. The semiconductor device includes a first transistor, an insulator covering the first transistor, and a second transistor over the insulator. The first transistor includes a first gate electrode, a second gate electrode overlapping with the first gate electrode, and a semiconductor between the first gate electrode and the second gate electrode. The first gate electrode is electrically connected to one of a source and a drain of the second transistor.Type: GrantFiled: October 26, 2017Date of Patent: June 16, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daigo Ito, Yutaka Okazaki, Takahisa Ishiyama
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Patent number: 10644039Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: GrantFiled: May 28, 2019Date of Patent: May 5, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
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Patent number: 10522690Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment.Type: GrantFiled: February 28, 2018Date of Patent: December 31, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Daisuke Matsubayashi, Yuichi Sato
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Patent number: 10522689Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.Type: GrantFiled: May 25, 2017Date of Patent: December 31, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
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Publication number: 20190355751Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: ApplicationFiled: May 28, 2019Publication date: November 21, 2019Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka OKAZAKI, Tomoaki Moriwaka, Shinya SASAGAWA, Takashi OHTSUKI
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Patent number: 10483402Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10?5 ?·m or more and 4.8×10?3 ?·m or less.Type: GrantFiled: March 30, 2017Date of Patent: November 19, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yutaka Okazaki
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Publication number: 20190341495Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.Type: ApplicationFiled: July 17, 2019Publication date: November 7, 2019Inventors: Shunpei YAMAZAKI, Akihisa SHIMOMURA, Yuhei SATO, Yasumasa YAMANE, Yoshitaka YAMAMOTO, Hideomi SUZAWA, Tetsuhiro TANAKA, Yutaka OKAZAKI, Naoki OKUNO, Takahisa ISHIYAMA
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Patent number: 10374097Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.Type: GrantFiled: January 9, 2018Date of Patent: August 6, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
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Publication number: 20190237584Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: ApplicationFiled: April 9, 2019Publication date: August 1, 2019Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
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Publication number: 20190229192Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator over a substrate, an oxide over the first insulator, a second insulator over the oxide, a conductor overlapping with the oxide with the second insulator therebetween, a third insulator in contact with a top surface of the oxide, a fourth insulator in contact with a top surface of the third insulator, a side surface of the second insulator, and a side surface of the conductor, and a fifth insulator in contact with a side surface of the fourth insulator, a side surface of the third insulator, and the top surface of the oxide. The third insulator has a lower oxygen permeability than the fourth insulator.Type: ApplicationFiled: January 15, 2019Publication date: July 25, 2019Inventors: Hiroki KOMAGATA, Naoki OKUNO, Yutaka OKAZAKI, Hiroshi FUJIKI
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Publication number: 20190221674Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: ApplicationFiled: March 28, 2019Publication date: July 18, 2019Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
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Patent number: 10304864Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: GrantFiled: September 19, 2017Date of Patent: May 28, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
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Patent number: 10276724Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: GrantFiled: July 7, 2016Date of Patent: April 30, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
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Patent number: 10249651Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.Type: GrantFiled: March 5, 2018Date of Patent: April 2, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Naoto Yamade, Yuhei Sato, Yutaka Okazaki, Shunpei Yamazaki