Patents by Inventor Yutaka Yamada

Yutaka Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8602654
    Abstract: A bearing temperature monitoring device and bearing device provided with the monitoring device composed so that occurrence of scratch on the rotation shaft supported by the bearing caused by a bearing temperature carrying member integrated in the bearing such that its top end surface faces the rotation shaft, are provided.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 10, 2013
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Takaaki Kaikogi, Kazuhiko Yamashita, Takashi Nakano, Yuichiro Waki, Motohisa Uesato, Yutaka Yamada
  • Patent number: 8574115
    Abstract: An electric power tool includes a cylindrical reducer case accommodating the speed reduction mechanism. The speed reduction mechanism includes a planetary gear train and a movable member which is axially slidable to be engaged with or disengaged from the planetary gear train. The electric power tool includes the reducer case including a slide hole formed through a sidewall of the reducer case and axially extended and a rotary plate which is rotatable around a periphery of the reducer case about the axis, the rotary plate including an operation slot formed axially obliquely and overlapped with the slide hole; a supporting member radially outwardly protruded from the movable member and extended through the slide hole and the operation slot; and a biasing unit for applying a pressing force to the supporting member in a moving direction of the supporting member when the rotary plate is rotated to a position.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Masatoshi Atsumi, Yutaka Yamada, Kenichiro Inagaki
  • Publication number: 20130222558
    Abstract: According to one embodiment, pixel processor includes: storage module; first adder; and second adder. Storage module stores initial parallax, initial coordinate, parallax difference, and coordinate difference. Initial parallax represents parallax of predetermined pixel. Initial coordinate represents coordinate of parallax image information of the predetermined pixel. Parallax difference is for calculating, from parallax of one pixel, parallax of other pixel. Coordinate difference is for calculating, from coordinate of parallax image information of one pixel, coordinate of parallax image information of other pixel. First adder adds the parallax difference to the initial parallax to calculate parallax of other pixel, and repeats adding the parallax difference to the calculated parallax to calculate parallax of each pixel.
    Type: Application
    Filed: December 20, 2012
    Publication date: August 29, 2013
    Inventors: Yutaka YAMADA, Masayuki Tokunaga, Tatsuo Saishu
  • Patent number: 8502277
    Abstract: A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided. It comprises a field-effect transistor 1A having a substrate 2, a source electrode 4 and a drain electrode 5 provided on said substrate 2, and a channel 6 forming a current path between said source electrode 4 and said drain electrode 5; wherein said field-effect transistor 1A comprises: an interaction-sensing gate 9 for immobilizing thereon a specific substance 10 that is capable of selectively interacting with the detection targets; and a gate 7 applied a voltage thereto so as to detect the interaction by the change of the characteristic of said field-effect transistor 1A.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: August 6, 2013
    Assignee: Japan Science and Technology Agency
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Patent number: 8499934
    Abstract: There is provided a package structure for packing a flat display unit which improves workability in taking a flat display unit out of a packing box. A lower cushioning material which supports a display portion of the flat display unit from below has a manual insertion portion so that the display portion can be held at a portion close to a lifting person's body when the display portion is taken out of a lower part of the packing box. A reinforcing rib is provided on a front side of the lower cushioning material to prevent damage to the lower cushioning material due to a reduction in strength. To prevent the lower cushioning material from being taken out together with the display portion when the display portion is taken out, a recess is provided in the lower cushioning material so that the recess is caught on a bending portion in the lower part when the display portion is taken out.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: August 6, 2013
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Teppei Tanaka, Yutaka Yamada, Shuji Kato
  • Patent number: 8445906
    Abstract: A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: May 21, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshito Konno, Yutaka Yamada
  • Patent number: 8432333
    Abstract: To provide a reliable high brightness and definition image display by inhibiting a possible increase in fan noise and promoting cooling of an upper, hot portion of a display panel module, various boards, and image processing electronic components, an image display includes a flat display panel module, a display surface side cover on a display surface side of the display panel module, a non display surface side cover on a non display surface side of the display panel module, a display driving board, a power supply board, and a cooling fan, wherein a case of the cooling fan is larger than a distance between the display panel module and the non display surface side cover in an area where the cooling fan is installed, and a first end of the case of the cooling fan closer to the non display surface-side cover is positioned above a second end of the case closer to the display panel module.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: April 30, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyuki Isoshima, Kohei Miyoshi, Mika Ri, Seiichi Sekiguchi, Yutaka Yamada
  • Patent number: 8429496
    Abstract: A decoding unit is arranged between a reading unit that reads data with an error correction code added from memory cells on a specific one of the first data lines and an output unit that selectively outputs certain data of the read out data. The decoding unit corrects any errors in the data read out by the reading unit in accordance with the error correction code. The data in which the errors are corrected by the decoding unit is written back in the memory cells on the specific first data line.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Yamada, Tatsunori Kanai
  • Patent number: 8421788
    Abstract: It is an object of the present invention to provide an image display apparatus which enables cost reduction while being free from electromagnetic interference problems. A power supply circuit comprises, on a single circuit board, an AC inlet to which a power cord is connected from an external AC power supply, a filter circuit to which an inductance element is connected to suppress leakage of electromagnetic waves to the outside of the image display apparatus, and a switch which switches on/off an AC output supplied from the filter circuit. The circuit board of the power supply circuit is entirely covered by electromagnetic shielding means to shield electromagnetic waves. The electromagnetic shielding means is composed of, for example, a first shielding section which surrounds the lateral side of the circuit board and a second shielding section which covers the upper side of the circuit board. The second shielding section is formed of a part of the flat section of a rear cover of the image display apparatus.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: April 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hidenao Kubota, Yuzo Nishinaka, Yuki Iwane, Yutaka Yamada, Katsunobu Kimura
  • Patent number: 8381831
    Abstract: A rotary impact tool includes a drive power source for producing rotational power, a drive shaft driven by the rotational power supplied from the drive power source, an output shaft operatively connected to the drive shaft for receiving the rotational power, an impact mechanism operatively couplable with the drive shaft. The rotary impact tool further includes a changeover unit for changing over an impact mode in which the impact mechanism is operated and a drill driver mode in which the rotational power produced by the drive power source is transferred to the output shaft without operating the impact mechanism and a multi-stage speed reduction mechanism for transferring the rotational power produced by the drive power source to the output shaft through the drive shaft at variable speeds in at least three speed modes including a low speed mode, a middle speed mode and a high speed mode.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: February 26, 2013
    Assignee: Panasonic Electric Works Power Tools Co., Ltd.
    Inventors: Fumiaki Sekino, Kenichiro Inagaki, Yutaka Yamada, Hiroyuki Tsubakimoto
  • Patent number: 8381072
    Abstract: A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Yutaka Yamada
  • Patent number: 8374021
    Abstract: According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Publication number: 20130024488
    Abstract: According to an embodiment, a semiconductor device includes an arithmetic device that includes a first storage unit that stores first device-control information for deciding an arithmetic processing to be executed next to an arithmetic processing currently being executed by an arithmetic device and a timing at which the arithmetic processing to be executed next to the arithmetic processing currently being executed by the arithmetic device is executed; and the arithmetic device that includes a second storage unit that stores second device-control information for deciding a content of an operation contained in an arithmetic processing.
    Type: Application
    Filed: September 26, 2012
    Publication date: January 24, 2013
    Inventors: Yutaka YAMADA, Takashi YOSHIKAWA, Shigehiro ASANO
  • Publication number: 20120312482
    Abstract: A method of peeling an electronic component. The method includes a step of, when the electronic component is adhered onto a first main surface of a tape member, bringing a bellowphragm into contact with a second main surface, which is the other main surface of the tape member; and a step of, after the bellowphragm is brought into contact with the second main face, deforming the bellowphragm and the tape member by supplying a fluid to the bellowphragm to thereby peel the electronic component from the tape member.
    Type: Application
    Filed: August 17, 2012
    Publication date: December 13, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yoshito KONNO, Yutaka YAMADA
  • Publication number: 20120311405
    Abstract: A cache memory has a data holding unit, having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.
    Type: Application
    Filed: August 13, 2012
    Publication date: December 6, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori Kanai, Yutaka Yamada
  • Patent number: 8320119
    Abstract: For improving a cooling efficiency of a display panel in a flat-type image display, various substrates and an image display element are disposed within a thin-sized housing thereof, including: a display panel; a chassis supporting the display panel from a rear surface side thereof; a front surface-side cover on a front side of the display panel; a rear surface-side cover on a rear side of the display panel; an image display element connected to the display panel; a display driver substrate connected to the display panel, and on a surface thereof opposite to the chassis are provided circuit parts; a power source substrate, supplying driving power to the display driver substrate and the image display element, and on a surface thereof opposite to the chassis are provided circuit parts thereof; and a first insulator board opposite to the display driver substrates and the power source substrate of the chassis.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 27, 2012
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Nobuyuki Isoshima, Kohei Miyoshi, Mika Ri, Yutaka Yamada, Toshihiro Tsutsui, Teppei Tanaka, Hidenao Kubota, Yuzo Nishinaka
  • Publication number: 20120286243
    Abstract: A field-effect transistor or a single electron transistor is used as sensors for detecting a detection target such as a biological compound. A substrate has a first side and a second side, the second side being opposed to the first side. A source electrode is disposed on the first side of the substrate and a drain electrode disposed on the first side of the substrate, and a channel forms a current path between the source electrode and the drain electrode. An interaction-sensing gate is disposed on the second side of the substrate, the interaction-sensing gate having a specific substance that is capable of selectively interacting with the detection target. A gate for applying a gate voltage adjusts a characteristic of the transistor as the detection target changes the characteristic of the transistor when interacting with the specific substance.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Publication number: 20120286763
    Abstract: A method of detecting a detection target using a sensor requires a sensor having a transistor selected from the group of field-effect transistors or single electron transistors. The transistor includes a substrate, a source electrode disposed on the substrate and a drain electrode disposed on the substrate, and a channel forming a current path between the source electrode and the drawing electrode; an interaction-sensing gate comprising a specific substance; and a voltage gate. The method includes (a) providing the detection target on the interaction-sensing gate; (b) setting the gate voltage in the voltage gate at a predetermined level; (c) selectively interacting the specific substance with the detection target; (d) when the detection target interacts with the specific substance, changing a gate voltage in the voltage gate to adjust a characteristic of the transistor; and (e) measuring a change in the characteristic of the transistor to determine a presence of the detection target.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Kazuhiko MATSUMOTO, Atsuhiko KOJIMA, Satoru NAGAO, Masanori KATOU, Yutaka YAMADA, Kazuhiro NAGAIKE, Yasuo IFUKU, Hiroshi MITANI
  • Patent number: 8279359
    Abstract: A flat panel display apparatus includes a plasma display panel, a power supply substrate, a signal processing substrate, a Y sustaining substrate, and an X sustaining substrate. The power supply substrate, the signal processing substrate, the Y sustaining substrate and the X sustaining substrate are arranged at a back of the plasma display panel. When viewing the plasma display panel from the back, the power supply substrate is arranged at a center portion of the plasma display panel, the Y sustaining substrate is arranged at one of a left and right side of the plasma display panel, the X sustaining substrate is arranged at the other of the left and right side, and the signal processing substrate is arranged under the X sustaining substrate. A circuit substrate other than the power supply substrate, the Y sustaining substrate, and the X sustaining substrate is arranged under the power supply substrate.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 2, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Teppei Tanaka, Yasushi Naito, Yasuhiro Tomita, Yoshiharu Yamashita, Yutaka Yamada, Kohei Miyoshi, Seiichi Sekiguchi
  • Publication number: 20120238454
    Abstract: A substrate for an oxide superconductor including: a metal base; an interlayer of MgO formed on the metal base by ion beam assisted deposition method (IBAD METHOD); and a cap layer that is formed directly on the interlayer and has a higher degree of crystal orientation than that of the interlayer, in which the interlayer of MgO is subjected to a humidity treatment prior to formation of the cap layer.
    Type: Application
    Filed: April 25, 2012
    Publication date: September 20, 2012
    Applicants: INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, FURUKAWA ELECTRIC CO., LTD., FUJIKURA LTD.
    Inventors: Masateru YOSHIZUMI, Hiroyuki FUKUSHIMA, Hideyuki HATAKEYAMA, Yutaka YAMADA, Hiroshi TOBITA, Teruo IZUMI