Patents by Inventor Yuzo Shimada

Yuzo Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6515324
    Abstract: A capacitor has a lower electrode, a dielectric thin film, an upper electrode, and an insulation cover layer formed on an insulation substrate made of an organic film or a ceramic material, and through holes formed at positions corresponding to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package, with electrodes for connection to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package provided within through holes. In a method for mounting the capacitor, the capacitor is interposed between a flip-chip connected semiconductor element and a mounting substrate.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventors: Akinobu Shibuya, Shintaro Yamamichi, Toru Mori, Takao Yamazaki, Yuzo Shimada
  • Publication number: 20020185718
    Abstract: A semiconductor package comprising an LSI chip, a chip bump, an interposer, and a BGA bump is mounted at a predetermined position of a printed wiring board having a core layer. A heat sink for dissipating heat generated from the LSI chip is installed within the core layer. Further, heat radiating vias for conveying heat generated from the LSI chip to the heat sink are provided within the printed wiring board so that the BGA bump in the LSI chip is thermally liked with the heat sink. The heat generated from the LSI chip is mainly dissipated through a route of chip bump→interposer→BGA bump→heat radiating via→heat sink. By virtue of the above construction, the semiconductor device packaging structure can reduce the packaging volume of the heat sink while providing satisfactory cooling capacity and, at the same time, can minimize the length of signal wiring between LSI chips.
    Type: Application
    Filed: March 4, 2002
    Publication date: December 12, 2002
    Inventors: Kazuyuki Mikubo, Sakae Kitajo, Yuzo Shimada
  • Patent number: 6486540
    Abstract: A three-dimensional semiconductor device includes a cylindrical heat sink, wherein a CPU is provided on a substantially center of an inner bottom surface of the cylindrical heat sink, semiconductor chips are respectively mounted on an outer peripheral surface and an inner peripheral surface of the cylindrical heat sink, and the CPU is connected to an upper heat sink.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: November 26, 2002
    Assignee: NEC Corporation
    Inventors: Naoji Senba, Takao Yamazaki, Yuzo Shimada
  • Patent number: 6477284
    Abstract: The present invention provides a photo-electric combined substrate comprising an electric interconnection part having an electric interconnection layer and an electric insulating layer as well as an optical waveguide part consisting of a core and a clad, where the electric insulating layer in the electric interconnection part and the optical waveguide part are made of the same material; a ceramic substrate comprising an optical device and an electric device where a ceramic substrate has a concave where the concave is filled with a resin, and where at least an optical device is mounted on the ceramic substrate while an electric device on the resin in the substrate concave; and an optical waveguide comprising a core and a clad having a refractive index lower than that of the core, where the core is made of a fluorene-unit-containing epoxy acrylate resin.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: November 5, 2002
    Assignee: NEC Corporation
    Inventors: Mikio Oda, Sakae Kitajo, Yuzo Shimada, Masataka Itoh, Yoshinobu Kaneyama, Masahiko Fujiwara
  • Publication number: 20020135064
    Abstract: Conductive balls are transferred from a pallet onto an array of conductive pads on a semiconductor chip by means of a transfer apparatus; the transfer apparatus includes a pallet formed with an array of recesses same in pattern as the array of conductive pads, a movable head formed with an array of vacuum holes and a driving mechanism for moving the head from an idle position onto the pallet and from the pallet to the semiconductor chip; when the head is moved to the pallet, the vacuum holes are connected to the recesses so as to confine the conductive balls in the narrow spaces; the vacuum is developed; then the conductive balls are traveled through the closed spaces to the vacuum holes; even if the conductive balls have been charged, the conductive balls are never attracted to the adjacent balls, and are surely captured by the vacuum holes.
    Type: Application
    Filed: March 25, 2002
    Publication date: September 26, 2002
    Applicant: NEC Corporation
    Inventors: Ichiro Hazeyama, Sakae Kitajo, Yuzo Shimada, Akeo Katahira, Jun Ishida, Masaru Terashima, Kazuhiko Futakami
  • Patent number: 6430327
    Abstract: After an optical element 6, and more preferably both an optical element 6 and an electrical element 7, are mounted on a substrate 1, an upper clad 5 of optical waveguide is formed, covering these elements, and thereby a structure of hermetic seal is achieved through the use of the upper clad 5.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: August 6, 2002
    Assignee: NEC Corporation
    Inventors: Yoshinobu Kaneyama, Masataka Ito, Masahiko Fujiwara, Sakae Kitajo, Mikio Oda, Yuzo Shimada
  • Patent number: 6422452
    Abstract: An apparatus for lining up micro-balls in accordance with the present invention includes: ball carrying pallets having a plurality of pits for holding the micro-balls, respectively, on its surface, a pallet holder for holding the ball carrying pallets, a lining-up container defining a sealed chamber in association with the pallet holder hermetically fitted thereto, a storing tank for storing liquid carrier in which micro-balls are dispersed, and applying/collecting device for communicating the storing tank with the lining-up container via a passage to supply the micro-balls together with the liquid carrier from the storing tank to the sealed chamber and return the surplus micro-balls together with the liquid carrier from the sealed chamber to the storing tank.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: July 23, 2002
    Assignee: Japan E M Co., Ltd.
    Inventors: Takumi Yamamoto, Kazuhiko Futakami, Akira Hatase, Nobuaki Takahashi, Naoji Senba, Yuzo Shimada
  • Publication number: 20020074643
    Abstract: A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.
    Type: Application
    Filed: November 28, 2001
    Publication date: June 20, 2002
    Inventors: Takao Yamazaki, Toru Mori, Akinobu Shibuya, Shintaro Yamamichi, Yuzo Shimada
  • Publication number: 20020070400
    Abstract: A capacitor has a lower electrode, a dielectric thin film, an upper electrode, and an insulation cover layer formed on an insulation substrate made of an organic film or a ceramic material, and through holes formed at positions corresponding to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package, with electrodes for connection to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package provided within through holes. In a method for mounting the capacitor, the capacitor is interposed between a flip-chip connected semiconductor element and a mounting substrate.
    Type: Application
    Filed: August 31, 2001
    Publication date: June 13, 2002
    Inventors: Akinobu Shibuya, Shintaro Yamamichi, Toru Mori, Takao Yamazaki, Yuzo Shimada
  • Publication number: 20020056922
    Abstract: A metal layer is formed on each surface of topside substrate electrodes on a substrate. Another metal layer is formed on each surface of chip electrodes on a function element chip. Both ends of vertical coil springs are connected to the topside substrate electrodes and the chip electrodes through the metal layers, respectively. In this way, the topside substrate electrodes are connected to the chip electrodes through the vertical coil springs by means of flip hip bonding.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 16, 2002
    Applicant: NEC Corporation
    Inventors: Takuo Funaya, Naoji Senba, Nobuaki Takahashi, Sakae Kitajyo, Yuzo Shimada
  • Patent number: 6378756
    Abstract: A solder ball arrangement device has a thin arrangement plate having a plurality of through-holes of a truncated pyramid shape, a porous member bonded to the arrangement plate, and a housing member for receiving the arrangement plate and the porous member for defining an air space inside the housing member. A suction pump is provided to evacuate the air space and to receive an array of solder balls in the through-holes by suction. The through-holes are formed by etching, and the porous member reinforces the thin arrangement plate.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: April 30, 2002
    Assignee: NEC Corporation
    Inventors: Nobuaki Takahashi, Naoji Senba, Yuzo Shimada
  • Publication number: 20020025623
    Abstract: A semiconductor device provided with a thin film capacitor having a small equivalent series inductance is provided, which can be operated at a high frequency range and contributes to size reduction of the electronic devices. The semiconductor device comprises a device formed on a silicon substrate 1a, interlayer insulating films 3a, 3b, and 3c, wiring blocks including a power source wire block and a ground wire block, and a thin film capacitor 14 formed on an uppermost insulating layer. The thin film capacitor 14 comprises a lower electrode 6 connected to the ground wire block 4e through a contact 5d, an upper electrode 8 which is connected to the power source wire block 4d through a contact 5d, and which extends above the lower electrode 6, and a dielectric layer 7 which is inserted between the lower and the upper electrodes.
    Type: Application
    Filed: July 11, 2001
    Publication date: February 28, 2002
    Applicant: NEC Corporation
    Inventors: Shintaro Yamamichi, Toru Mori, Akinobu Shibuya, Takao Yamazaki, Yuzo Shimada
  • Publication number: 20020022303
    Abstract: A three-dimensional semiconductor device includes a cylindrical heat sink, wherein a CPU is provided on a substantially center of an inner bottom surface of the cylindrical heat sink, semiconductor chips are respectively mounted on an outer peripheral surface and an inner peripheral surface of the cylindrical heat sink, and the CPU is connected to an upper heat sink.
    Type: Application
    Filed: April 11, 2001
    Publication date: February 21, 2002
    Inventors: Naoji Senba, Takao Yamazaki, Yuzo Shimada
  • Publication number: 20020017700
    Abstract: The present invention provides a multilayer capacitor advantageously used as a decoupling capacitor having sufficient capacitance, low self inductance, and a high LC resonance frequency, and a semiconductor device and an electric circuit board that use the same. The electric circuit board of the present invention uses as a decoupling capacitor a three lead multilayer capacitor having a structure wherein a feed-through electrically connected to the power source line of an LSI is surrounded by two internal electrodes connected to a ground line via a dielectric layer. A multilayer capacitor can be used in which a plurality of holes 8, 9, and 10 are provided on a capacitor chip where the plurality of dielectric layers 7 and the plurality of electrode layers 11 and 12 are alternately multilayer, and dielectric parts are provided that electrically connect to a portion of the electrode layers on the internal surface of a portion of the holes among the plurality of holes.
    Type: Application
    Filed: July 5, 2001
    Publication date: February 14, 2002
    Applicant: NEC Corporation
    Inventors: Toru Mori, Akinobu Shibuya, Shintaro Yamamichi, Takao Yamazaki, Yuzo Shimada
  • Publication number: 20010054762
    Abstract: A semiconductor device includes (a) a semiconductor chip, (b) a patterned lead composed of an electrical conductor and formed on the semiconductor chip in electrical contact with the semiconductor chip, and (c) a resin film sealing a main surface of the semiconductor chip therewith. The lead has a portion projecting beyond the main surface of the semiconductor chip.
    Type: Application
    Filed: May 23, 2001
    Publication date: December 27, 2001
    Applicant: NEC Corporation
    Inventors: Takao Yamazaki, Naoji Senba, Yuzo Shimada
  • Publication number: 20010015372
    Abstract: An apparatus for transferring micro-balls in accordance with the present invention, includes a suction head in which a plurality of suction pits are open for holding the respective micro-balls, a head holder to which the suction head is detachably coupled, a suction device communicating with a suction chamber in the head holder, for allowing the suction pits to hold the micro-balls by decompressing the interior of the suction chamber, and a holder transporting device to which the head holder is mounted, wherein the holder transporting device are movable between a sucking position at which is placed a pallet on which the micro-balls to be held by the suction pits, a transferring position at which is placed a working object to which the micro-balls held by the suction pits, and a head exchanging position at which the replacement of the suction head is carried out relative to the head holder.
    Type: Application
    Filed: December 5, 2000
    Publication date: August 23, 2001
    Applicant: E .M Co., Ltd.,
    Inventors: Takumi Yamamoto, Kazuhiko Futakami, Akira Hatase, Nobuaki Takahashi, Naoji Senba, Yuzo Shimada
  • Publication number: 20010009261
    Abstract: An apparatus for lining up micro-balls in accordance with the present invention includes: ball carrying pallets having a plurality of pits for holding the micro-balls, respectively, on its surface, a pallet holder for holding the ball carrying pallets, a lining-up container defining a sealed chamber in association with the pallet holder hermetically fitted thereto, a storing tank for storing liquid carrier in which micro-balls are dispersed, and applying/collecting device for communicating the storing tank with the lining-up container via a passage to supply the micro-balls together with the liquid carrier from the storing tank to the sealed chamber and return the surplus micro-balls together with the liquid carrier from the sealed chamber to the storing tank.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 26, 2001
    Applicant: Japan E M Co., Ltd.
    Inventors: Takumi Yamamoto, Kazuhiko Futakami, Akira Hatase, Nobuaki Takahashi, Naoji Senba, Yuzo Shimada
  • Patent number: 6188127
    Abstract: In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: February 13, 2001
    Assignee: NEC Corporation
    Inventors: Naoji Senba, Yuzo Shimada, Kazuaki Utsumi, Kenichi Tokuno, Ikushi Morizaki, Akihiro Dohya, Manabu Bonkohara
  • Patent number: 6130111
    Abstract: A packaged semiconductor device includes an LSI chip, a chip size package integrally bonded to the LSI chip to mount and hold the LSI chip thereon in order to connect an electrode of a board on which the LSI chip is to be mounted and an electrode of the LSI chip to each other, an electrode formed on a surface of the package opposite to a surface thereof which is bonded to the LSI chip, so as to be connected to the electrode of the board, at least one through hole formed to extend through the LSI chip and the package, and a connecting conductor formed to extend through the through hole in order to connect the electrode of the package and the electrode of the LSI package to each other.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: October 10, 2000
    Assignee: NEC Corporation
    Inventors: Kazuhiro Ikuina, Yuzo Shimada, Kazuaki Utsumi
  • Patent number: 6111479
    Abstract: A laminate printed circuit board loaded with transistors, ICs (Integrated Circuits) or LSIs (Large Scale Integrated Circuits) and a method of producing the same are disclosed. The circuit board includes a signal layer, a ground layer and a power supply layer sequentially laminated with the intermediary of insulation layers. An impedance adding circuit is formed in the power supply layer. A magnetic layer is positioned at least above or at least blow the impedance adding circuit. The circuit board with this configuration reduces power supply noise to a noticeable degree.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: August 29, 2000
    Assignee: NEC Corporation
    Inventors: Osamu Myohga, Shiro Yoshida, Mitsuo Saito, Yuzo Shimada, Hirokazu Tohya, Ryo Maniwa