Abstract: A solder ball arrangement device has a thin arrangement plate having a plurality of through-holes of a truncated pyramid shape, a porous member bonded to the arrangement plate, and a housing member for receiving the arrangement plate and the porous member for defining an air space inside the housing member. A suction pump is provided to evacuate the air space and to receive an array of solder balls in the through-holes by suction. The through-holes are formed by etching, and the porous member reinforces the thin arrangement plate.

Abstract: A fabrication method of a plastic-molded lead component is provided, in which leads are aligned at a fine pitch of approximately 100 .mu.m or less with a high accuracy, a simplified process sequence, and a low cost. First, a template having opened V-grooves is prepared. The V-grooves extend along a straight line and are aligned in parallel at a fixed pitch. Second, wire pieces are placed in the respective grooves of the template. Third, the placed pieces of the wire pieces are aligned in parallel on the template at a same pitch as that of the grooves. Fourth, a molding compound is supplied onto the template with or without the use of a mold to bury the aligned wire pieces placed in the grooves. Fifth, the molding compound supplied onto the template is cured to form an encapsulation plastic on the template. The wire pieces placed in the grooves are encapsulated by the encapsulation plastic in such a way that both ends of the wire pieces are exposed from opposite sides of the encapsulation plastic.

Abstract: An electronic device assembly (and method for forming the same) including a first substrate having a first surface, a second surface, and a first pad on the first surface thereof; a second substrate having a first surface, a second surface, and a second pad on the second surface thereof, the first pad facing the second pad; a rigid spherical core interposed between the first and second pads; and solder connecting the first and second pads. The first substrate has a through-hole which is provided through the first substrate at a position of the first pad, at least a part of the solder is positioned in the through-hole and at least a part of the spherical core is received in the through-hole. The through-hole has an inner wall which is continuously tapered from the first surface of the first substrate to the second surface of the first substrate.

Abstract: A multilayer glass ceramic substrate having a plurality of conductor layers each laminated through a glass ceramic layer. The glass ceramic layer has a composition comprising of alumina, borosilicate magnesium glass and cordierite crystal produced by chemical reaction between alumina and borosilicate magnesium glass. The content of alumina is 12 to 59.6 wt %, the content of borosilicate magnesium glass is 18 to 69.6 wt %, the content of the cordierite crystal is 1 to 50 wt % and the sum of components is 100 wt %. The multilayer glass ceramic substrate shows improved mechanical strength.

Abstract: An insulative magnetic layer is disposed between a power source conductor layer and a ground conductor layer of a printed-wiring board. Two pieces of conductors are formed by cutting out a part of the power source conductor layer. Another two pieces of conductors are formed by cutting out a part of the ground conductor layer. The former conductors and the latter conductors are connected by five viaholes. A spiral coil inductor of a spiral form is formed in this way. This inductor has the strengthened inductance owing to the insulative magnetic layer provided therein.

Abstract: A method for arranging metallic balls to form an array of bump electrodes comprises the steps of immersing a silicon template in ethanol dropping metallic balls through the ethanol onto the template to receive the metallic balls in the holes of the template. The metallic balls are free from cohesion caused by electrostatic charge or moisture. The template may be inclined in the ethanol. The holes are formed by anisotropic etching a silicon plate.

Abstract: A three-dimensional memory module includes a plurality of semiconductor device units, every adjacent two of which are stack-connected via through-holes by a bump connecting method. Each of the plurality of semiconductor device units includes a carrier having a circuit pattern and the through-holes connected to the circuit pattern. The semiconductor device unit also includes at least one semiconductor memory chip mounted on the carrier such that the semiconductor memory chip is connected to the circuit pattern, and at least one chip select semiconductor chip mounted on the carrier to be connected to the circuit pattern such that the chip select semiconductor chip can select the semiconductor memory chip.

Abstract: A packaged semiconductor device includes an LSI chip, a chip size package integrally bonded to the LSI chip to mount and hold the LSI chip thereon in order to connect an electrode of a board on which the LSI chip is to be mounted and an electrode of the LSI chip to each other, an electrode formed on a surface of the package opposite to a surface thereof which is bonded to the LSI chip, so as to be connected to the electrode of the board, at least one through hole formed to extend through the LSI chip and the package, and a connecting conductor formed to extend through the through hole in order to connect the electrode of the package and the electrode of the LSI package to each other.

Abstract: An IC package includes an IC chip substrate having a first surface on which a plurality of electrodes are formed, and an organic substrate having a first surface on which a plurality of bump electrodes are provided. The organic substrate is combined with the IC chip substrate. Each of the bump electrodes is in contact with a corresponding one of the electrodes on the IC chip substrate. The organic substrate has a plurality of through holes and metallization patterns electrically connecting each of the bump electrodes to a corresponding one of the through holes.

Abstract: An electronic device assembly includes a rigid, first substrate and a second substrate. The first substrate has a first pad on the upper surface, and a through-hole at a position of the first pad. The second substrate has a second pad on the upper surface thereof. The first and second pads are connected via solder. At least a part of the solder is positioned in the through-hole of the first substrate. The first substrate may include a flexible substrate and a rigid plate. The through-hole is provided in the flexible substrate. The first pad is provided on the lower surface of the flexible substrate. The rigid plate is attached to the flexible substrate. The plate has a hole at a position of the through-hole to make the first pad reachable.

Abstract: An electronic package includes a supporting member, an electronic device, a carrier, a substrate a cooling means. The supporting member includes a plate and a bottom leg for supporting the plate. A first end of the bottom leg is joined to the lower surface of the plate. The carrier has a hole for receiving the bottom leg. The electronic device is connected to the carrier and is attached to the lower surface of the plate. A second end of the bottom leg is inserted into the hole of the carrier. The second end of the bottom leg is joined to the upper surface of the substrate. The electronic device is positioned between the plate of the supporting member and the substrate. The cooling is attached onto and supported by the upper surface of the plate.

Abstract: This invention relates to an interconnection structure comprising one or more insulating films and one or more layers of conductor electrode patterns, wherein at least one of the insulating films consists of a fluorene skeleton-containing epoxy acrylate resin, and to a method of making a multilayer interconnection structure including the steps of roughening the surface of an insulating resin layer and forming a conductor thereon by electroless plating, wherein the average roughness (Ra), maximum roughness (Ry) and conductor thickness (T) of the roughened surface of the insulating resin layer satisfy the following relations:0.2.ltoreq.Ra.ltoreq.0.6 (unit: .mu.m) (1)0.02.ltoreq.Ra/T.ltoreq.0.2 (2)0.05.ltoreq.Ry/T.ltoreq.0.

Abstract: An electronic package according to the present invention comprises a supporting member, an electronic device, a carrier, a substrate and cooling means. The supporting member includes a plate and a bottom leg for supporting the plate. A first end of the bottom leg is joined to the lower surface of the plate. The carrier has a hole for receiving the bottom leg. The electronic device is connected to the carrier and is attached to the lower surface of the plate. A second end of the bottom leg is inserted into the hole of the carrier. The second end of the bottom leg is joined to the upper surface of the substrate. The electronic device is positioned between the plate of the supporting member and the substrate. The cooling means is attached onto and supported by the upper surface of the plate.

Abstract: An organic insulation film has inner leads electrically connecting a conductor thereof with an LSI chip. The inner leads are connected to pads on the periphery of the LSI chip. The connecting portions between the inner leads and the pads of the LSI chip are sealed by casting a plastic seal. The plastic seal extends over the back side of the organic insulative film. The projected portion of the plastic seal at the back side of the organic insulative film is covered with a moisture-proofing seal member to provide more inexpensive than transfer molding and highly reliable seal structure for a tape carrier package.

Abstract: The invention provides a semiconductor device including a semiconductor substrate formed thereon with at least one recessed portion, an electrically conductive layer covering at least a surface of the recessed portion therewith, and a ball-bump formed on the electrically conductive layer within the recessed portion. The semiconductor device can act as a probe card by additionally having a tester device formed in the semiconductor substrate and provided with a function of testing electrical performances of a semiconductor device. Since the recessed portion can be formed by lithography technique, it is possible to arrange the greater number of pins in a smaller pitch, and in addition, it is also possible to locate ball-bumps in place with higher accuracy than a conventional semiconductor device.

Abstract: A multilayer glass ceramic substrate having a plurality of conductor layers each laminated through a glass ceramic layer. The glass ceramic layer has a composition comprising of alumina, borosilicate magnesium glass and cordierite crystal produced by chemical reaction between alumina and borosilicate magnesium glass. The content of alumina is 12 to 59.6 wt %, the content of borosilicate magnesium glass is 18 to 69.6 wt %, the content of the cordierite crystal is 1 to 50 wt % and the sum of components is 100 wt %. The multilayer glass ceramic substrate shows improved mechanical strength.

Abstract: In a first step, a first substrate is prepared. The first substrate has a first surface, a second surface, and a through-hole therebetween. In a second step, a second substrate is prepared. The second substrate has a first surface, a second surface, and a pad on the first surface of the second substrate. In a third step, a solder is provided on the pad of the second substrate. In a fourth step, the through-hole of the first substrate is positioned on the solder. The second surface of the first substrate and the first surface of the second substrate face each other. In a fifth step, the solder is heated to flow the solder into the through-hole of the first substrate. In the sixth step, an appearance of the solder on the first surface of the first substrate may be confirmed for detection of a connection of the solder.

Abstract: A ceramic substrate comprises a ceramic body and a wiring pattern made of silver series selectively formed on the major face of the ceramic body. The ceramic body contains silver particles of 0.1 to 2.5 percents.

Abstract: A low temperature sintering, low dielectric inorganic composition is a ternary inorganic composition comprising cordierite, quartz glass and lead borosilicate glass, wherein if the amounts of the cordierite, quartz glass and lead borosilicate glass are represented by X, Y and Z (wt %) respectively, the composition of the ternary system falls within the range encircled by the following four points (a) to (d) including the lines between each neighboring two points:(X=35; Y=0; Z=65) (a)(X=65; Y=0; Z=35) (b)(X=0; Y=65; Z=35) (c)(X=0; Y=35; Z=65) (d)The inorganic composition has a dielectric constant substantially lower than that of the conventional composition while maintaining high reliability such as an ability of being sintered at a low temperature, high insulation properties and high resistance to water as well as excellent mechanical properties such as strength.

Abstract: A process for manufacturing a hybrid multilayer ceramic wiring substrate having a low dielectric constant includes a conductor wiring forming step and an insulating layer forming step. The conductor wiring forming step comprises the steps of: applying a photoresist upon a multilayer ceramic wiring substrate in which a plurality of conductor layers are laminated via insulation layers formed of a low temperature sinterable ceramic composition having a low dielectric constant; exposing the photoresist to light and developing the exposed photoresist to form a mask pattern; and selectively plating the mask pattern. The insulating layer forming step comprises the steps of: printing a photo-setting paste for an insulating layer on the substrate and drying the paste; forming a via hole pattern by light exposure and development using a mask; and burying and sintering a conductor paste into via holes.