Patents by Inventor Yuzo Shimada

Yuzo Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4724283
    Abstract: A multi-layer circuit board is disclosed which includes a plurality of AlN ceramic layers stocked and combined as an integrated form and wiring layers interposed at different levels between the AlN ceramic layers. The wiring layers are made of a mixture of tungsten and AlN ceramic particles, the content of the AlN ceramic particles being 0.5 to 2.0 wt. %. A plurality of through-holes are formed in the AlN ceramic layers to interconnect the wiring layers formed at different levels.
    Type: Grant
    Filed: September 29, 1986
    Date of Patent: February 9, 1988
    Assignee: NEC Corporation
    Inventors: Yuzo Shimada, Yasuhiro Kurokawa, Kazuaki Utsumi
  • Patent number: 4574255
    Abstract: Between insulative layers (31-37, 41-44), a multilayer substrate comprises at least one dielectric layer (26-29). It is possible to form capacitors (58), resistors (46), and wiring conductors (61, 62) in the substrate. The at least one dielectric layer should be of at least one dielectric composition which has a perovskite structure. Preferably, each insulative layer is of an insulating material which consists essentially of aluminum oxide and lead borosilicate glass. The substrate is convenient in manufacturing a crystal oscillator by mounting a crystal vibrator (71) and a transistor (72) on the principal surface(s). Examples of the dielectric composition are:Pb[(Fe.sub.2/3.W.sub.1/3).sub.0.33 (Fe.sub.1/2.Nb.sub.1/2).sub.0.67 ]O.sub.3,Pb[(Mn.sub.1/3.Nb.sub.2/3).sub.0.01 (Mg.sub.1/2.W.sub.1/2).sub.0.30 (Ni.sub.1/3.Nb.sub.2/3).sub.0.49 Ti.sub.0.20 ]O.sub.3,andPb[(Mg.sub.1/2.W.sub.1/2).sub.0.66 Ti.sub.0.34 ]O.sub.3.
    Type: Grant
    Filed: December 15, 1983
    Date of Patent: March 4, 1986
    Assignee: NEC Corporation
    Inventors: Shuzo Fujii, Yuzo Shimada, Kazuaki Utsumi, Yutaka Saito
  • Patent number: 4567542
    Abstract: A multilayer ceramic substrate with an interlayered capacitor has a large electrostatic capacity and a high flexural strength, such as 1,500 Kg/cm.sup.2 or more, and yet is manufactured at a relatively low firing or sintering temperature. A first ceramic body includes a plurality of laminated first ceramic sheets with a high dielectric constant and with a plurality of internal electrodes sandwiching the respective first ceramic sheets to form capacitors therebetween. A second ceramic body is laminated over one side of the first ceramic body and has a plurality of laminated second ceramic sheets with a low dielectric constant. A plurality of first wiring layers are sandwiched between the second ceramic sheets. A third ceramic body is laminated over the other side of the first ceramic body and has a plurality of laminated third ceramic sheets formed of the same ceramic material that is used to make the second ceramic sheets. The second and third ceramic bodies are thicker than the first ceramic body.
    Type: Grant
    Filed: April 23, 1984
    Date of Patent: January 28, 1986
    Assignee: NEC Corporation
    Inventors: Yuzo Shimada, Kazuaki Utsumi, Teruyuki Ikeda, Masanori Suzuki
  • Patent number: 4536435
    Abstract: A multilayer glass-ceramic substrate comprises insulator layers of a composition consisting essentially of, when components are expressed as oxides in percent by weight, 40-60 percent of aluminum oxide, 1-40 percent of lead oxide, 1-30 percent of boron oxide, 2-40 percent of silicon dioxide, 0.01-25 percent of at least one oxide of chemical element(s) of Group II of the periodic table, and 0.01-10 percent of at least one oxide of Group IV element(s) except carbon, silicon, and lead. Each insulator layer may be only from 190 microns down to 10 microns thick. The substrate has a flexural strength of 2,100 kg/cm.sup.2 or more. Preferably, the Group II element(s) is magnesium, calcium, strontium, barium, and/or zinc. The Group IV element(s) is zirconium, titanium, germanium, and/or tin. When the percentages are 40-60 for aluminum oxide, 4.1-16.6 for lead oxide, 1.0-10.0 for boron oxide, 14.0-39.1 for silicon dioxide, 0.1-4.8 for magnesium oxide, 2.0-10.0 for calcium oxide, 0.05-3.0 for barium oxide, 0.01-3.
    Type: Grant
    Filed: October 14, 1982
    Date of Patent: August 20, 1985
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kazuaki Utsumi, Yuzo Shimada, Masanori Suzuki, Hideo Takamizawa