Patents by Inventor Yves Martin

Yves Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10613023
    Abstract: A sensor housing apparatus includes a housing having an enclosure and outer assembly, at least one flow path extending through the housing, a gas sensor disposed in the enclosure and a thermal mass. The thermal mass is mounted within the enclosure in thermal communication with the gas sensor, and is configured to transfer thermal energy from the gas sensor to an ambient environment surrounding the housing and minimize temperature gradients adjacent the gas sensor.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yves Martin, William Green, Theodore G. van Kessel
  • Publication number: 20200100369
    Abstract: Solder-pinning metal pads for electronic components and techniques for use thereof to mitigate de-wetting are provided. In one aspect, a structure includes: a substrate; and a solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof. For instance, the sidewalls can be present at edges of the solder pad, or inset from the edges of the solder pad. The sidewalls can be vertical or extend up from the solder pad at an angle. The sidewalls can be formed from the same material or a different material as the solder pad. A method is also provided that includes forming a solder pad on a substrate, the solder pad comprising sidewalls extending up from a surface thereof.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Yves Martin, Tymon Barwicz
  • Patent number: 10562242
    Abstract: There is provided a method for applying thermosetting tape on contoured resilient surfaces off an object which comprises biasing selected section(s) of the resilient member to minimize tape and object distortion. There is also provided a tape laying apparatus configured to enable the optimization of automatic tape application on resilient contoured surfaces and minimize tape and object distortion.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: February 18, 2020
    Assignee: MI INTEGRATION S.E.N.C.
    Inventors: Yves Martin, Claude Houle, Yannick Longpré, Nicolas Nadeau
  • Publication number: 20200023561
    Abstract: An injection mold for encapsulating a substrate comprises a lower mold component and an upper mold component adapted to form an encapsulation mold at an edge of the substrate when the upper mold component engages the lower mold component. The lower mold component comprises a substrate support and wherein the upper mold component comprises a recess. The injection mold includes a tiltable insert sized and shaped to slide within the recess to form a seal for the encapsulation mold, the insert having a substrate-contacting surface defining an area of the substrate contacted by the insert. The injection mold includes a plurality of pressure-exerting actuators connected to the tiltable insert and each being configured to independently apply pressure on the substrate via the insert, wherein the plurality of pressure-exerting actuators are adapted to equilibrate a total predetermined pressure exerted by the insert substantially evenly across the area of the substrate-contacting surface.
    Type: Application
    Filed: December 1, 2017
    Publication date: January 23, 2020
    Inventors: Nicolas NADEAU, Jean THERRIEN, Yves MARTIN
  • Patent number: 10527787
    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yves Martin, Jason S. Orcutt, Tymon Barwicz, William Green
  • Publication number: 20200002252
    Abstract: The present invention relates to a process for producing high-purity para-xylene, comprising a single step of separation by adsorption in an SMB, with a subsequent step of separation by distillation in a first three-fraction distillation column producing at least two raffinates and optionally of two isomerization steps, making it possible to improve the overall para-xylene yield of the aromatic loop and to minimize the economic impact.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Applicant: AXENS
    Inventors: Isabelle PREVOST, Jerome PIGOURIER, Pierre-Yves MARTIN, Arnaud COTTE
  • Publication number: 20200003952
    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Yves Martin, Jason S. Orcutt, Tymon Barwicz, William Green
  • Publication number: 20190391329
    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
    Type: Application
    Filed: February 8, 2019
    Publication date: December 26, 2019
    Inventors: Yves Martin, Jason S. Orcutt, Tymon Barwicz, William Green
  • Publication number: 20190391330
    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 26, 2019
    Inventors: Yves Martin, Jason S. Orcutt, Tymon Barwicz, William Green
  • Patent number: 10465947
    Abstract: A cooler operating according to the Stirling cycle, including a housing including a compression cylinder and a regeneration cylinder, a movable compression piston and a movable regeneration piston, that can move in translational motion in the compression cylinder and in the regeneration cylinder, a driving crankshaft, including a rotating crank pin, and two connecting rods coupled to the compression piston and the regeneration piston, the connecting rods being coupled to the rotating crank pin, a fluid flow duct for circulating fluid, connecting the compression cylinder and the regeneration cylinder, one end of the fluid flow duct being disposed on the regeneration piston, and the fluid flow duct including a deformable pipe that is deformed in accordance with the movement of the compression piston and/or of the regeneration piston.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 5, 2019
    Assignee: THALES
    Inventor: Jean-Yves Martin
  • Patent number: 10444429
    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yves Martin, Jason S. Orcutt, Tymon Barwicz, William Green
  • Patent number: 10393962
    Abstract: A method for assembling a semiconductor device includes: receiving a first chip including a plurality of first bonding pads, a first standoff and a second standoff, wherein a first solder is deposited on each of the first bonding pads; depositing a second solder on each of the first and second standoffs; arranging a second chip over the first chip, wherein the second chip includes a plurality of second bonding pads, and at least one of the second bonding pads has a corresponding first bonding pad; heating the second chip over a melting point of the second solder to melt the second solder, and placing the second chip on the first chip to touch and solidify the second solder on each of the first and second standoffs; performing a reflow process to melt the first solder on each of the first bonding pads so that at least one of the first solders touches a corresponding second bonding pad; and waiting a predetermined period of time to allow the second chip to move until a side edge of the second chip touches a wav
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tymon Barwicz, Yves Martin, Jae-Woong Nah
  • Publication number: 20190219554
    Abstract: A gas sensor enclosure is provided. The gas sensor enclosure includes at least two coaxial shells, a gas sensor, a gas permeable membrane that exposes a portion of the gas sensor to gas exchange through one of the at least two coaxial shells and a screen. The screen encloses the at least two coaxial shells, the gas sensor and the gas permeable membrane.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: JOSEPHINE B CHANG, YVES MARTIN, THEODORE G. VAN KESSEL
  • Publication number: 20190162902
    Abstract: A method for assembling a semiconductor device includes: receiving a first chip including a plurality of first bonding pads, a first standoff and a second standoff, wherein a first solder is deposited on each of the first bonding pads; depositing a second solder on each of the first and second standoffs; arranging a second chip over the first chip, wherein the second chip includes a plurality of second bonding pads, and at least one of the second bonding pads has a corresponding first bonding pad; heating the second chip over a melting point of the second solder to melt the second solder, and placing the second chip on the first chip to touch and solidify the second solder on each of the first and second standoffs; performing a reflow process to melt the first solder on each of the first bonding pads so that at least one of the first solders touches a corresponding second bonding pad; and waiting a predetermined period of time to allow the second chip to move until a side edge of the second chip touches a wav
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Tymon Barwicz, Yves Martin, Jae-Woong Nah
  • Patent number: 10302859
    Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yves Martin, Jason S. Orcutt, Tymon Barwicz, William Green
  • Publication number: 20190043112
    Abstract: A method for providing product information to at least one media displaying device located in at least one store and having an output and a data reception unit, each store having at least one data emitting device, comprising the steps of: generating, at a central back-office server connected to the store data emitting unit, an individual glyph corresponding to each different character or symbol of the product information; generating at least a display script comprising reference and position data of the glyphs in the product information; transmitting the display script and the individual glyphs to the store data emitting device; transmitting the display script to the media displaying device; broadcasting the individual glyphs; selecting and loading in the media displaying device individual glyphs corresponding to the reference data comprised in the display script; and displaying the selected and loaded individual glyphs at the output means of the media displaying device according to the position data comprise
    Type: Application
    Filed: October 10, 2018
    Publication date: February 7, 2019
    Applicant: SES-imagotag
    Inventor: Yves Martin
  • Patent number: 10131849
    Abstract: The present invention describes a process for the isomerization of a light naphtha with a view to forming high octane number gasolines, said process using a deisopentanizer and a deisohexanizer which are thermally integrated in a manner such as to reduce the consumption of the high temperature utilities employed in the process.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: November 20, 2018
    Assignee: AXENS
    Inventors: Isabelle Prevost, Laurent Watripont, Pierre-Yves Martin, Jerome Pigourier
  • Patent number: 10113121
    Abstract: The present invention describes a process for the production of high octane number gasoline by isomerization of a light naphtha cut, comprising two separation steps located downstream of the reaction step which can be used to improve the energy efficiency of said process.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 30, 2018
    Assignee: AXENS
    Inventors: Jerome Pigourier, Isabelle Prevost, Laurent Watripont, Pierre-Yves Martin
  • Publication number: 20180250892
    Abstract: There is provided a method for applying thermosetting tape on contoured resilient surfaces off an object which comprises biasing selected section(s) of the resilient member to minimize tape and object distortion. There is also provided a tape laying apparatus configured to enable the optimization of automatic tape application on resilient contoured surfaces and minimize tape and object distortion.
    Type: Application
    Filed: September 20, 2016
    Publication date: September 6, 2018
    Applicant: MI INTEGRATION S.E.N.C.
    Inventors: Yves MARTIN, Claude HOULE, Yannick LONGPRÉ, Nicolas NADEAU
  • Patent number: 10031713
    Abstract: A method for displaying product information on at least one electronic label having a graphic display and a data reception unit is disclosed. The method includes: generating, at a server connected to the label, an individual glyph corresponding to each different character or symbol of the product information; generating at least a display script comprising reference and position data of said glyphs in the product information; transmitting the display script to the label; broadcasting the individual glyphs; selecting and loading in the label individual glyphs corresponding to the reference data comprised in the display script and displaying the selected and loaded individual glyphs according to the position data comprised in the display script. A server, an electronic label and a sever thereof are also provided.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: July 24, 2018
    Assignee: SES-imagotag
    Inventor: Yves Martin