Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Abstract: Systems, methods, and circuitries are provided for extending the range of an analog-to-digital converter (ADC) associated with interference cancellation. In one example a transceiver includes front end circuitry configured to transmit a radio frequency (RF) transmit signal that includes an intended signal and an interference signal. The transceiver includes self-interference cancellation (SIC) circuitry configured to control the front end circuitry based at least on a digital baseband reference transmit signal that comprises a digital representation of the intended signal.

Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Abstract: Systems, methods, and circuitries are provided for resonator-based local oscillator signal generation for receiving self-interference signals. An interference cancellation system for a transceiver includes a resonator configured to generate a high-frequency signal and a local oscillator circuitry. The local oscillator circuitry includes a digital-to time converter configured to receive the high-frequency signal and, in response, generate a clock signal for receiving an interfering signal having an interference frequency. Digital cancellation circuitry is configured to adapt operation of the transceiver based, at least in part, on the received interfering signal.

Abstract: Systems, methods, and circuitries are provided for extending the range of an analog-to-digital converter (ADC) associated with interference cancellation. In one example a transceiver includes front end circuitry configured to transmit a radio frequency (RF) transmit signal that includes an intended signal and an interference signal. The transceiver includes self-interference cancellation (SIC) circuitry configured to control the front end circuitry based at least on a digital baseband reference transmit signal that comprises a digital representation of the intended signal.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

Abstract: Systems, methods, and circuitries are provided for resonator-based local oscillator signal generation for receiving self-interference signals. An interference cancellation system for a transceiver includes a resonator configured to generate a high-frequency signal and a local oscillator circuitry. The local oscillator circuitry includes a digital-to time converter configured to receive the high-frequency signal and, in response, generate a clock signal for receiving an interfering signal having an interference frequency. Digital cancellation circuitry is configured to adapt operation of the transceiver based, at least in part, on the received interfering signal.

Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Abstract: A radio frequency signal synthesizer circuit includes a digital to analog converter configured to generate an analog output signal for each clock cycle of a clock signal to provide the radio frequency signal and a controlled oscillator to generate the clock signal. The controlled oscillator is configured to vary a cycle time of the clock signal for a radio frequency signal in a first frequency range in a first operation mode or to maintain a constant cycle time for a radio frequency signal in a second frequency range in a second operation mode, the second frequency range being different than the first frequency range.

Abstract: One embodiment covers an apparatus for generating a transmission signal. The apparatus may include a signal generator that generates a first signal with a first frequency spectrum comprising a carrier frequency; a power control unit that provides a power information signal which represents a signal level of the transmission signal residing at the carrier frequency; a first signal shaper for noise-shaping the first signal based on the power information signal to form a second signal which has a noise component in at least one frequency range remote from the carrier frequency, the noise component of the second signal being from one or more signal components associated with the carrier frequency; and a signal output that provides the second signal in the form of a transmission signal.

Abstract: A radio frequency signal synthesizer circuit includes a digital to analog converter configured to generate an analog output signal for each clock cycle of a clock signal to provide the radio frequency signal and a controlled oscillator to generate the clock signal. The controlled oscillator is configured to vary a cycle time of the clock signal for a radio frequency signal in a first frequency range in a first operation mode or to maintain a constant cycle time for a radio frequency signal in a second frequency range in a second operation mode, the second frequency range being different than the first frequency range.

Abstract: This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.

Abstract: An apparatus comprises a mechanical resonator-based oscillator module generating a local oscillator signal with a frequency of more than 700 MHz. Further, the apparatus comprises a digital-to-time converter module generating a frequency adapted signal based on the local oscillator signal.

Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Abstract: Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.

Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Abstract: An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.

Abstract: Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.