Abstract: A computer system to track and enhance performance of a virtual workspace system is provided. The computer system receives requests to profile phases of a distributed process executed by hosts coupled to one another via a network. Each of phase includes operations executed by processes hosted by the hosts. Each of phase either starts with receipt of a request via a user interface of a virtualization client or ends with provision of a response to the request via the user interface. The computer system identifies event log entries that each include an identifier of an event marking a start or an end of one of the operations, constructs a performance profile based on the event log entries, and transmits the performance profile to the user interface.

Abstract: Methods and systems for automated application launching are described herein. A computing device may receive a message, the message indicative of an application for a given event and a time in which to launch the application for the given event, from a client device. Based on the content of the message, the computing device may generate a plurality of text strings based on content of the message. The computing device may identify the application based on a comparison of the plurality of text strings with one or more entries of a database of applications and may launch the application in response to the identification of the application and at the time indicated in the received message, so as to make ready the application for use for the given event.

Abstract: The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.

Abstract: A semiconductor substrate includes: an active region; and a termination region surrounding the active region, and the semiconductor device includes: a first main electrode provided on the active region; a second main electrode provided on an opposite side of the first main electrode; an impurity region provided on an outermost periphery of the termination region; a first insulating film provided on an outer end edge part; a second insulating film provided on a region from an inner end edge part of the termination region to an end edge part of the active region; a first semi-insulating film covering a region from part of the impurity region which is not covered by the first insulating film to a partial upper side of the first insulating film; and a second semi-insulating film covering a region from the first semi-insulating film to a partial upper side of the first main electrode.

Abstract: A computer system to track and enhance performance of a virtual workspace system is provided. The computer system receives requests to profile phases of a distributed process executed by hosts coupled to one another via a network. Each of phase includes operations executed by processes hosted by the hosts. Each of phase either starts with receipt of a request via a user interface of a virtualization client or ends with provision of a response to the request via the user interface. The computer system identifies event log entries that each include an identifier of an event marking a start or an end of one of the operations, constructs a performance profile based on the event log entries, and transmits the performance profile to the user interface.

Abstract: A PET detecting module may include a scintillator array configured to receive a radiation ray and generate optical signals in response to the received radiation ray. The scintillator array may have a plurality of rows of scintillators arranged in a first direction and a plurality of columns of scintillators arranged in a second direction. A first group of light guides may be arranged on a top surface of the scintillator array along the first direction. The light guide count of the first group of light guides may be less than the row count of the plurality of rows of scintillators. A second group of light guides may be arranged on a bottom surface of the scintillator array. The light guide count of the second group of light guides may be less than the column count of the plurality of columns of scintillators.

Abstract: Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region. of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view.

Abstract: A method and system for using in a Positron Emission Tomography (PET) system. The PET system comprises at least one processor and a storage. The PET system comprises an acquisition module and a processing module. The acquisition module is configured to acquire a PET data set corresponding to a target object. The acquisition module comprises a first light sensor array, a second light sensor array, and a scintillator array. The processing module is configured to determine a three-dimensional position of an incidence photon based on the PET data set. The first number of light sensors in the first light sensor array and the second number of light sensors of the second light sensor array is less than the number of scintillator of the scintillator array.

Abstract: The present disclosure relates to a power supply grounding fault protection circuit. A power supply grounding fault protection circuit may include a power supply circuit, a leakage grounding detection circuit, a signal amplifying and shaping circuit, a microcontroller control circuit, a power supply detection and indicator circuit, a tripping mechanism control circuit, a reverse grounding detection and execution circuit, a wireless network circuit, and an automatic resetting circuit. The practice of the present disclosure may permit a user to reset the grounding fault circuit interrupter remotely after a leaking fault of a circuit is eliminated.

Abstract: In one example, a hybrid circuit interrupter may include a three-coil architecture, first coil circuitry, leakage detection circuitry, and a main processing circuit including a processor. The three-coil architecture may include a coil housing, three coils, and a plurality of coil assembly conductors. The coils may be disposed within the coil housing. The coils may be parallel and aligned. The coil assembly conductors may be at least partially disposed within the coil housing. The first coil circuitry may be connected to the first coil and may generate first coil signals. The leakage detection circuitry may be connected to the other coils and may generate a leakage signal. The processor may receive the first coil and leakage signals, determine whether an arc fault exists from the first coil signals, determine whether a ground fault exists from the leakage signal, and generate a first trigger signal if a fault is determined.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: In one example, a hybrid circuit interrupter may include a three-coil architecture, first coil circuitry, leakage detection circuitry, and a main processing circuit including a processor. The three-coil architecture may include a coil housing, three coils, and a plurality of coil assembly conductors. The coils may be disposed within the coil housing. The coil assembly conductors may be at least partially disposed within the coil housing. The first coil circuitry may be connected to the first coil and may generate first coil signals. The leakage detection circuitry may be connected to the other two coils and may generate a leakage signal. The processor may receive the first coil signals, receive the leakage signal, determine whether an arc fault exists based on the first coil signals, determine whether a ground fault exists based on the leakage signal, and generate a first trigger signal if a fault is determined to exist.

Abstract: A semiconductor device includes gate trenches and dummy gate trenches formed on the upper surface side of a semiconductor substrate, gate electrodes embedded in the gate trenches, dummy gate electrodes embedded in the dummy gate trenches, a channel layer formed in the surface portion on the upper surface side of the semiconductor substrate, a carrier storage layer formed below the channel layer, and a collector layer formed on the lower surface side of the semiconductor substrate. A relationship D4<D1<D3<D2 holds true, where D1 is the depth of the bottoms of the gate electrodes, D2 is the depth of the bottoms of the dummy gate electrodes, D3 is the depth of the bottom of the carrier storage layer, and D4 is the depth of the junction between the channel layer and the carrier storage layer.

Abstract: The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.

Abstract: A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.

Abstract: A PET detecting module may include a scintillator array configured to receive a radiation ray and generate optical signals in response to the received radiation ray. The scintillator array may have a plurality of rows of scintillators arranged in a first direction and a plurality of columns of scintillators arranged in a second direction. A first group of light guides may be arranged on a top surface of the scintillator array along the first direction. The light guide count of the first group of light guides may be less than the row count of the plurality of rows of scintillators. A second group of light guides may be arranged on a bottom surface of the scintillator array. The light guide count of the second group of light guides may be less than the column count of the plurality of columns of scintillators.

Abstract: A strain and acoustic wave testing device includes an acoustic wave transmitting terminal, an upper pressure-bearing shaft, corundum ejector pins, an upper displacement slide, a lower displacement slide, a heat insulation shell, a carbon fiber sleeve, a rock sample, a lower pressure-bearing shaft, an acoustic wave receiving terminal, a lower copper electrode, pearl powder, a temperature sensor, a transformer, a temperature-acoustic wave control box, an oscilloscope, an upper copper electrode, and a data collection and processing system.

Abstract: A method and system for using in a Positron Emission Tomography (PET) system. The PET system comprises at least one processor and a storage. The PET system comprises an acquisition module and a processing module. The acquisition module is configured to acquire a PET data set corresponding to a target object. The acquisition module comprises a first light sensor array, a second light sensor array, and a scintillator array. The processing module is configured to determine a three-dimensional position of an incidence photon based on the PET data set. The first number of light sensors in the first light sensor array and the second number of light sensors of the second light sensor array is less than the number of scintillator of the scintillator array.