Abstract: A ground fault circuit interrupter includes a reset key, a reset mechanism, a conductive assembly configured to connect a power supply input side to a load side, a leakage signal detection circuit, and an electromagnetic tripping mechanism. The reset mechanism comprises a reset support and a support return mechanism. The reset support comprises a reset bracket and a support reset spring. The support return mechanism comprises a reset pole, a reset key spring, a compression spring, a reset block, a compression spring container, a reset slider, and a contact conductive part. The contact conductive part is disposed at a lower end of the reset slider and is configured to align with a position of a switch contact on a first PCB board. A state of contact or separation between the contact conductive part and the switch contact is configured to control an on-off state of the conductive assembly.

Abstract: In one example, an arc fault circuit interrupter (AFCI) is provided. The AFCI may include a plurality of current arc signature detection blocks configured to output a plurality of corresponding current arc signatures, and a processor. The processor may be configured to receive each of the plurality of current arc signature from each of plurality of current arc signature detection blocks, respectively, and generate a first trigger signal. The processor may be further configured to assess each of the current arc signatures, determine whether an arc fault exists based on the assessment, and generate the first trigger signal if an arc fault is determined to exist. A method for detecting an arc fault is also provided.

Abstract: In one example, a hybrid circuit interrupter may include a three-coil architecture, first coil circuitry, leakage detection circuitry, and a main processing circuit including a processor. The three-coil architecture may include a coil housing, three coils, and a plurality of coil assembly conductors. The coils may be disposed within the coil housing. The coil assembly conductors may be at least partially disposed within the coil housing. The first coil circuitry may be connected to the first coil and may generate first coil signals. The leakage detection circuitry may be connected to the other two coils and may generate a leakage signal. The processor may receive the first coil signals, receive the leakage signal, determine whether an arc fault exists based on the first coil signals, determine whether a ground fault exists based on the leakage signal, and generate a first trigger signal if a fault is determined to exist.

Abstract: A method of fabricating transition metal dichalcogenides includes a preparing step, a steaming step and a depositing step. The preparing step is performed for providing a transition metal substrate, a reactive gas and a solid chalcogenide. The steaming step is performed for heating the solid chalcogenide to generate a chalcogenide gas in a steaming space. The depositing step is performed for introducing the reactive gas into the chalcogenide gas to ionize the chalcogenide gas so as to generate a chalcogenide plasma in a depositing space. The depositing step is performed under a process vacuum pressure from low vacuum pressure to atmospheric pressure. The reactive gas and the chalcogenide gas are flowed from top to bottom through a top of the transition metal substrate. The loading substrate is heated at a loading substrate temperature, and the steaming space is different from the depositing space.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: The disclosure relates to a system and method for evaluating and calibrating detector in a scanner, further evaluating and calibrating time information detected by at least one time-to-digital convertor.

Abstract: A clamp apparatus includes a mounting module, a clamp module, and an actuator. The clamp module includes two facing arms and a cam clamped between the two arms. Each arm is rotatably mounted to the mounting module and has a clamp end. The clamp module is configured to have a clamped configuration in which each clamp end is engaged with the object and an open configuration in which the object is free from each of the clamp ends, and further configured to operate between the clamped configuration and the open configuration. The actuator is configured to drive the cam thereby imparting motive force to the two arms during the operation between the clamped configuration and the open configuration.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: The disclosure relates to a system and method for evaluating and calibrating detector in a scanner, further evaluating and calibrating time information detected by at least one time-to-digital convertor.

Abstract: The present disclosure relates to a power supply grounding fault protection circuit. A power supply grounding fault protection circuit may include a power supply circuit, a leakage grounding detection circuit, a signal amplifying and shaping circuit, a microcontroller control circuit, a power supply detection and indicator circuit, a tripping mechanism control circuit, a reverse grounding detection and execution circuit, a wireless network circuit, and an automatic resetting circuit. The practice of the present disclosure may permit a user to reset the grounding fault circuit interrupter remotely after a leaking fault of a circuit is eliminated.

Abstract: A semiconductor device includes: a semiconductor substrate; a device region on the semiconductor substrate; a planar edge termination region on the semiconductor substrate to surround the device region; and a passivation film covering the edge termination region, wherein the passivation film includes a semi-insulating film directly contacting the semiconductor substrate.

Abstract: The disclosure relates to a system and method for evaluating and calibrating detector in a scanner, further evaluating and calibrating time information detected by at least one time-to-digital convertor.

Abstract: A ground fault circuit interrupter includes a reset key, a reset mechanism, a conductive assembly configured to connect a power supply input side to a load side, a leakage signal detection circuit, and an electromagnetic tripping mechanism. The reset mechanism comprises a reset support and a support return mechanism. The reset support comprises a reset bracket and a support reset spring. The support return mechanism comprises a reset pole, a reset key spring, a compression spring, a reset block, a compression spring container, a reset slider, and a contact conductive part. The contact conductive part is disposed at a lower end of the reset slider and is configured to align with a position of a switch contact on a first PCB board. A state of contact or separation between the contact conductive part and the switch contact is configured to control an on-off state of the conductive assembly.

Abstract: An insulated gate bipolar transistor having a gate electrode (7) and an emitter electrode (9) is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer (18) is provided below an N type drift layer (1) in the transistor region. A P type collector layer (19) is provided below the first N type buffer layer (18). A second N type buffer layer (20) is provided below the N type drift layer (1) in the termination region. A collector electrode (21) is directly connected to the P type collector layer (19) and the second N type buffer layer (20). An impurity concentration of the second N type buffer layer (20) decreases as a distance from the collector electrode (21) decreases. The second N type buffer layer (20) does not form any ohmic contact with the collector electrode (21).

Abstract: A planar MOSFET is provided on the upper surface of the N?-type semiconductor substrate in a mesa portion between the trenches. A P+-type emitter layer is provided between the trench and the planar MOSFET in the mesa portion. A P-type collector layer is provided on a lower surface of the N?-type semiconductor substrate. The planar MOSFET includes an N+-type emitter layer, an upper portion of the N?-type semiconductor substrate, a P-type base layer, and a planar gate on the foregoing with a gate insulating film interposed therebetween. The planar gate is connected to the gate trench. The P+-type emitter layer has a higher impurity concentration than the P-type base layer and has an electric potential equal to an emitter potential of the N+-type emitter layer. The N+-type emitter layer is not in contact with the trench. A trench MOSFET is not formed.

Abstract: A planar MOSFET is provided on the upper surface of the N?-type semiconductor substrate in a mesa portion between the trenches. A P+-type emitter layer is provided between the trench and the planar MOSFET in the mesa portion. A P-type collector layer is provided on a lower surface of the N?-type semiconductor substrate. The planar MOSFET includes an N+-type emitter layer, an upper portion of the N?-type semiconductor substrate, a P-type base layer, and a planar gate on the foregoing with a gate insulating film interposed therebetween. The planar gate is connected to the gate trench. The P+-type emitter layer has a higher impurity concentration than the P-type base layer and has an electric potential equal to an emitter potential of the N+-type emitter layer. The N+-type emitter layer is not in contact with the trench. A trench MOSFET is not formed.

Abstract: A method of fabricating transition metal dichalcogenides includes a preparing step, a steaming step and a depositing step. The preparing step is performed for providing a transition metal substrate, a reactive gas and a solid chalcogenide. The steaming step is performed for heating the solid chalcogenide to generate a chalcogenide gas in a steaming space. The depositing step is performed for introducing the reactive gas into the chalcogenide gas to ionize the chalcogenide gas so as to generate a chalcogenide plasma in a depositing space. The depositing step is performed under a process vacuum pressure from low vacuum pressure to atmospheric pressure. The reactive gas and the chalcogenide gas are flowed from top to bottom through a top of the transition metal substrate. The loading substrate is heated at a loading substrate temperature, and the steaming space is different from the depositing space.

Abstract: A ground fault circuit interrupter includes a reset key, a reset mechanism, a conductive assembly configured to connect a power supply input side to a load side, a leakage signal detection circuit, and an electromagnetic tripping mechanism. The reset mechanism comprises a reset support and a support return mechanism. The reset support comprises a reset bracket and a support reset spring. The support return mechanism comprises a reset pole, a reset key spring, a compression spring, a reset block, a compression spring container, a reset slider, and a contact conductive part. The contact conductive part is disposed at a lower end of the reset slider and is configured to align with a position of a switch contact on a first PCB board. A state of contact or separation between the contact conductive part and the switch contact is configured to control an on-off state of the conductive assembly.

Abstract: The present invention relates to a ground fault protection circuit and a ground fault circuit interrupter. A ground fault protection circuit may include a power supply circuit, a ground fault detection circuit, a signal amplifying and shaping circuit, a microcontroller control circuit, a power supply detection and indicator circuit, a tripping mechanism control circuit, and a reverse grounding detection and execution circuit. A ground fault circuit interrupter may comprise an interrupter body with a ground fault protection circuit in the interrupter body. The practice of the present disclosure may address installation safety risks of conventional ground fault circuit interrupters and arc fault circuit interrupter and improve the safety of ground fault circuit interrupters.

Abstract: Smart power socket comprising an MCU, a power supply circuit connected to the MCU, a wireless module circuit, and a drive switch control circuit, where the power supply circuit is connected to a low voltage power line, the wireless module circuit is connected to an external control device by means of wireless communication, and the drive switch control circuit is controlled by the MCU to implement controlling of on and off states of the smart power socket. Further, a smart home system comprising a remote control terminal and the smart power socket, where the smart power socket constitutes a LAN and is connected to Internet by means of a smart home gateway, and the remote control terminal is connected to the smart power socket by means of Internet to implement remote controlling of a household appliance plugged into the smart power socket.