Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.

Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.

Abstract: The applicant provides a compound for enhancing the space coupling degree of an endothelial cell ion channel complex TRPV4-KCa2.3 and anti-hypertension applications thereof. By finding the structural domains of the interacting sites of the endothelial cell ion channel complex TRPV4-KCa2.3, a compound with specificity which can act at the two interacting sites is prepared in the present invention. It is found that the compound can enhance the space coupling degree of the TRPV4-KCa2.3 complex and has great significance for the research and development of anti-hypertension drugs.

Abstract: The present disclosure provides methods and apparatus to improve the dynamic coherent length of a sweep velocity-locked laser pulse generator (SV-LLPG) in an all-electronic fashion. A digital SV-LLPG is disclosed with two operation modes, i.e., unidirectional and bidirectional sweep modes; self-adaptive and time-dependent loop parameters (gain and location of poles/zeros); and, self-adaptive initial input curve. High frequency locking architectures, both single-side band (SSB) modulation method and direct phase measurement method, are provided to suppress the linewidth, or improve the coherent length, of the swept laser. A combination of high and low frequency locking, or a combination of multiple architectures disclosed in this invention, is utilized to achieve a higher level of linewidth reduction.

Abstract: A driving method is provided to drive an LCD panel having rows of pixels includes obtaining source data signals of a plurality of frames for the LCD panel; inputting a source data signal of one frame of the plurality of frames; and inverting polarity of the source data signal of the one frame before scanning sequentially the rows of pixels. The driving method also includes configuring at least one of timing of the source data signal and timing of scanning a first row of the rows of pixels to cause a time overlap between an actual scanning time of the first row and a time period when the source data signal is at a threshold value to be no less than an original scanning time of the first row; scanning the first row of the rows of pixels; and scanning rest of the rows of pixels to complete displaying the one frame.

Abstract: The present application discloses a display apparatus including a display panel; a backlight module; a motion sensor for detecting a motion parameter of the display apparatus and generating a motion parameter signal representing the motion parameter; at least one signal processor for comparing the motion parameter with a threshold value, and generating a power off signal if the motion parameter is greater than the threshold value; and a controller for controlling a state of the backlight module; the controller is configured to control the backlight module in a power off state upon receiving the power off signal.

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

Abstract: The present disclosure provides methods and apparatus to improve the dynamic coherent length of a sweep velocity-locked laser pulse generator (SV-LLPG) in an all-electronic fashion. A digital SV-LLPG is disclosed with two operation modes, i.e., unidirectional and bidirectional sweep modes; self-adaptive and time-dependent loop parameters (gain and location of poles/zeros); and, self-adaptive initial input curve. High frequency locking architectures, both single-side band (SSB) modulation method and direct phase measurement method, are provided to suppress the linewidth, or improve the coherent length, of the swept laser. A combination of high and low frequency locking, or a combination of multiple architectures disclosed in this invention, is utilized to achieve a higher level of linewidth reduction.

Abstract: A device and a method for producing high-purity nano molybdenum trioxide are provided. The device comprises a raw material bin (1), a feeding machine (2), a subliming furnace (7), a first vent tube (24), a second vent tube (25), a spraying device (23) and a filtering assembly. The sublimated molybdenum trioxide is cooled with clean and dehumidified air so as to finally obtain the nano molybdenum trioxide, and the recycling mode is reliable, pollution-free and high in efficiency.

Abstract: The present invention relates to the novel flavor and fragrance use of 2,6-dipropyl-5,6-dihydro-2H-thiopyran-3-carbaldehyde.

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

Abstract: The present invention relates to the technology of material surface modification and the preparation adsorption new material, which involves the preparation of CQDs and the application of CQDs on modifying water purification function material. Firstly, the CQDs with rich functional groups and specific graphene structure has been prepared based on the low-cost biomass. Then, modified the traditional adsorbent by prepared CQDs under the in situ synthesis process. Secondly, synthesis the CQDs basic on the organic waste-water under low-temperature hydrothermal treatment process. Then, prepared the CQDs modified water purification material by collecting the CQDs under the flocculation process. This invention can be used in the widely used in the field of modification and preparation of functional materials, because of it not only gives a new method to synthesis low-cost and high performance water purification material, but also provide a new idea to treat high toxicity and refractory organic waste-water.

Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.

Abstract: A device remote access method includes receiving, by a bus filter driver on a thin client (TC) side, a request for remote access by a virtual machine (VM) side to a physical device on the TC side, converting, by the bus filter driver, the request for remote access into a remote operation instruction that may be read by a physical device driver, and sending, by the bus filter driver, the remote operation instruction to the physical device driver, where the remote operation instruction is used to instruct the physical device driver to drive the physical device to execute a read/write operation and return remote response data that carries an execution result of the read/write operation which implements remote access by the VM side to the physical device on the TC side, and because a device driver is not modified, the TC side may continue to normally access the physical device.

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract: A touch screen includes a touch panel and an ultrasonic probe. A touch panel includes a cover plate, a first sensing structure including a plurality of receiving electrode lines, and a second sensing structure including a plurality of transmitting electrode lines. The ultrasonic probe includes a first piezoelectric film and a second piezoelectric film. The first piezoelectric film is attached to the touch panel and electrically coupled to the receiving electrode line, and the second piezoelectric film is attached to the touch panel and electrically coupled to the transmitting electrode line. An electronic device is also provided.

Abstract: A touch screen includes a touch panel and an ultrasonic probe. A touch panel includes a cover plate, a first sensing structure including a plurality of receiving electrode lines, a glass sheet, and a second sensing structure including a plurality of transmitting electrode lines. The ultrasonic probe includes a first piezoelectric film and a second piezoelectric film. The first piezoelectric film is attached to the touch panel and electrically coupled to the receiving electrode line, and the second piezoelectric film is attached to the touch panel and electrically coupled to the transmitting electrode line. An electronic device is also provided.

Abstract: A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.

Abstract: An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.