Abstract: One or more computer-readable media store instructions that cause one or more processors to transmit a request for content, receive a first content item and a second content item associated with the first content item, and display the first content item within a content slot in an information resource. The content slot has a first size occupying a first region of the information resource. The operations further include identifying a user interaction associated with the first content item and, responsive to the user interaction, expanding the content slot from the first size to a second size and displaying, in the expanded content slot, the first content item, the second content item, and an actionable object configured to reduce the content slot from the second size to the first size. The second size occupies the first region and an adjoining second region of the information resource.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region. A surface of the first region of the semiconductor substrate contains a gate structure, a surface of the second region of the semiconductor substrate contains a dummy gate structure, and the semiconductor substrate under the dummy gate structure contains an isolation structure. The semiconductor structure further includes a bulk layer having a substantially flat reshaped surface formed in the semiconductor substrate at each of two sides of the gate structure; and a protective layer formed on the reshaped surface of the bulk layer.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: Video messaging systems and methods utilize a video messaging component based on a video messaging component container stored in a data store. The video messaging component container includes a collaborative video list that shows a list of video content generated by users of the video messaging component. Iterations of the video messaging component are rendered in host applications on client devices. As video content is generated by the iterations, the collaborative video list is updated to include the video content, and the iterations of the video messaging component are updated to reflect changes to the collaborative video list in real-time.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.

Abstract: A semiconductor structure includes a conductive layer, an IMD layer and a plurality of protrusions. The IMD layer is formed on the conductive layer and has a first etch rate. Each protrusion includes an etching slowing layer, a lower electrode and a MTJ layer, wherein the etching slowing layer is formed on the IMD layer and has a second etch rate, the lower electrode passes through the IMD layer and the etching slowing layer, and the MTJ layer is formed on the lower electrode. The second etch rate is less than the first etch rate.

Abstract: The present disclosure relates to integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. A bottom electrode via is surrounded by one or more interior sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding a conductive core. A bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. The barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

Abstract: Provided is a construction method for a fully prefabricated multi-story concrete plant, the construction method may achieve full coverage of a hoisting operation of the large beam and column prefabricated components of a floor by employing a single intelligent hoisting robot, an angle change of the track devices, an angle change of a moving device, and a self-lifting device. It is not necessary to arrange a transition track at the turn of the installation route, which saves space and installation cost, and overcomes the disadvantage of high cost caused by the traditional prefabricated construction mode of multi-story concrete plant, which needs to arrange a plurality of large hoisting equipment. It may achieve the mechanization and intelligence of the whole construction process of the fully prefabricated multi-story concrete plant.

Abstract: A method includes receiving from a client device a request for content, and transmitting to the client device a first content item, a second content item, and a script for displaying the first and second content items within an information resource. The script includes instructions that cause the client device to (1) display the first content item within a content slot having a first size occupying a first region of the information resource, (2) identify a user interaction associated with the first content item, (3) expand, responsive to the user interaction associated with the first content item, the content slot from a first size to a second size, and (4) display, responsive to the user interaction and in the expanded content slot, the first content item and the second content item and an actionable object configured to reduce the content slot from the second size to the first size.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. A bottom electrode via surrounded by one or more interior sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding a conductive core. A bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. The barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.