Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: The present invention discloses a lithium ion battery with low capacity loss, which comprises an cathode material, a anode material and an electrolyte. The cathode material has a chemical formula Li(9x+2y+z)MnyMezO(3y+z)N2xX3x (xLi9N2X3·yLi2MnO3·zA), and has advantages such as stable performance, low surface residue, and high dilithiation capacity. The preparation of the cathode material comprises the steps of: synthesis of a precursor from a metal salt and a manganese compound by chemical co-precipitation, followed by, sequentially, heat treatment and crushing; and repeated lithium supplementation and multi-stage sintering to form the cathode material. The method for preparing the cathode material is simple. By repeated lithium supplementation and sintering, Li3N is inserted into the lattice of the material. Li9N2X3 forms a eutectic with the base material, which further reduces the surface residue, improves the storage and cycling performance of the material.

Abstract: The present invention discloses a lithium ion battery with high capacity, which comprises an cathode material, a anode material and an electrolyte. The cathode material has a chemical formula LiNi(1-x)MexO, wherein x is 10?6 to 10?1, and Me is a third metal other than Li and Ni. Said material has the advantages of high purity, high density and high delithiation capacity. The preparation method of the cathode material comprises: subjecting a nickel salt and an additive to chemical co-precipitation, calcining, and inducing of a crack structure with an inducing environment, an inducing chemical, or a combination thereof to give a precursor, which is mixed with Li2O, sintered and crushed to give the cathode material.

Abstract: One or more servers can implement a method including generating an information resource comprising a content package including first content, metadata of a content extension, and a script for displaying the first content, and transmitting the information resource to a client device to cause the client device to: display the first content within an inline frame; identify an interaction with a user interface feature; transmit, responsive to identifying the interaction, a content extension request based on the metadata of the content extension; receive, responsive to the content extension request, a second content item; responsive to identifying the interaction, expand the inline frame from the first size to a second size; and display, in the expanded inline frame, the second content item, the second content item different from the first content item.

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Abstract: A semiconductor structure includes two source/drain features spaced apart from each other, at least one channel feature disposed between the two source/drain features, a gate dielectric layer disposed on the at least one channel feature, a gate feature, and an electrically conductive capping feature. The gate feature is disposed on the gate dielectric layer and has a first surface, a second surface which is opposite to the first surface, and an interconnect surface which interconnects the first and second surfaces. The electrically conductive capping feature is in direct contact with one of the first and second surfaces of the gate feature, and extends beyond the interconnect surface of the gate feature. Methods for manufacturing the semiconductor structure are also disclosed.

Abstract: Disclosed are a method and apparatus for detecting a near-field object, a medium and an electronic device. In the present disclosure, the characteristics of an automatic exposure apparatus before and after light supplement of a light supplement lamp are used, two images are shot in the same direction before and after light supplement of the light supplement lamp, and whether the near-field object exists is determined through comparison of the two images. Without adding additional apparatuses, the task of discovering the near-field objects by a self-walking device is completed by using the existing apparatus, and the collision between the self-walking device and the near-field object is avoided.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: The invention relates to a seating frame for a vehicle seat, the frame comprising a back frame component for supporting a back rest, wherein the back frame component includes a plurality of interconnected reinforcing ribs that form a single unit, and wherein the seating frame is a one-piece injection-molded part made of plastic material. The invention also relates to a process of making such a seating frame. Furthermore, the invention relates to a vehicle seat comprising such a seating frame, and a vehicle comprising such a vehicle seat or such a seating frame.

Abstract: A semiconductor device and the manufacturing method thereof are described. The device includes semiconductor channel sheets, source and drain regions and a gate structure. The semiconductor channel sheets are arranged in parallel and spaced apart from one another. The source and drain regions are disposed beside the semiconductor channel sheets. The gate structure is disposed around and surrounding the semiconductor channel sheets. The silicide layer is disposed on the source region or the drain region. A contact structure is disposed on the silicide layer on the source region or the drain region. The contact structure includes a metal contact and a liner, and the silicide layer is in contact with the metal contact, and the liner is separate from the silicide layer by the metal contact.

Abstract: A semiconductor device includes nanostructures vertically arranged and spaced apart from one another along a first direction. The semiconductor device also includes a dielectric fin structure of a dielectric material of uniform composition and an isolation structure on opposite sides of the nanostructures. Moreover, the semiconductor device also includes a gate structure wrapping around the nanostructures. The gate structure extends between the nanostructure and the dielectric fin structure, and extends between the nanostructures and the isolation structure. Furthermore, the nanostructures are spaced apart from the dielectric fin structure along a second direction perpendicular to the first direction by a first distance, and from the isolation structure along the second direction by a second distance, where the first distance is greater than the second distance. Additionally, the gate structure interfaces with the dielectric fin structure on a surface extending perpendicular to the first direction.

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Abstract: The present disclosure is directed to enhancing a lumen display in a CT sectional image of a blood vessel. The CT sectional image may be displayed with a first window level. An average CT value of lumen sections near the heart may be obtained, and a highest CT value of a section of a current blood vessel may also be obtained. A window level may be determined based on the average CT value and the highest CT value. At least a part of the section of the current blood vessel may then be displayed with the window level. The techniques allow for a window level to be preset to enhance lumen display and to improve the consistency of delineating the lumen contour, thereby avoiding deviations caused by subjective selection while saving time and improving patient flow.

Abstract: A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A method is provided for forming a memory device on a backside portion of a wafer substrate. In one step, a circuit device is formed on a frontside portion of the wafer substrate. In one step, the wafer substrate is etched to form a substrate indentation that exposes a portion of a circuit device. In one step, a memory device is formed, at least in part, in the substrate indentation.

Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a channel member having a longitudinal axis in a first direction, and the channel member has a first portion and a second portion separated from each other by a blank region. The semiconductor structure also includes a first gate structure formed over the blank region and having a longitudinal axis in a second direction different from the first direction and an isolation structure formed in the blank region and abutting the first gate structure in the second direction. The semiconductor structure also includes a through via structure formed through the isolation structure. In addition, the through via structure includes a first conductive filling layer, and a first air gap is sandwiched between the first conductive filling layer and the isolation structure.