Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.

Abstract: A device includes semiconductor device structure includes a first dielectric layer. A first plurality of nanostructures are disposed on the first dielectric layer, with the first plurality of nanostructures overlying one another. A first source/drain region is disposed laterally adjacent to a first side of the first plurality of nanostructures. A second dielectric layer is on a first side of the first source/drain region. A front side source/drain contact is disposed on a second side of the first source/drain region that is opposite the first side, and a backside source/drain contact is disposed on the first side of the first source/drain region. The backside source/drain contact extends through the second dielectric layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: A method of providing an ad extension includes selecting an advertisement for display. The method also includes selecting additional information related to the advertisement. The method also includes transmitting data representing the advertisement to a browser. The browser interacts with an expandable API to render an inline frame having an advertisement slot. The browser renders and displays the advertisement in the frame. The method also includes transmitting display data representing the additional information related to the advertisement to the browser. The browser receives an input to activate the ad extension. In response to the input, the browser interacts with the expandable API system to expand and render the frame. The browser renders, in the frame, the advertisement slot containing the advertisement. The browser also renders, in the frame, the additional information. The browser displays the expanded inline frame, such that the displayed frame covers a portion of the content.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate, a source/drain contact disposed over the substrate, a first dielectric layer disposed on the source drain contact, an etch stop layer disposed on the first dielectric layer, and a source/drain conductive layer disposed in the etch stop layer and the first dielectric layer. The structure further includes a spacer structure disposed in the etch stop layer and the first dielectric layer. The spacer structure surrounds a sidewall of the source/drain conductive layer and includes a first spacer layer having a first portion and a second spacer layer adjacent the first portion of the first spacer layer. The first portion of the first spacer layer and the second spacer layer are separated by an air gap. The structure further includes a seal layer.

Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. A bottom electrode via surrounded by one or more interior sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding a conductive core. A bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. The barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.

Abstract: A semiconductor structure (MG) includes a metal gate structure disposed over a semiconductor substrate, a dielectric layer disposed adjacent to the MG, a source/drain (S/D) feature disposed adjacent to the dielectric layer, and a S/D contact disposed over the S/D feature. The S/D contact includes a first metal layer disposed over the S/D feature and a second metal layer disposed on the first metal layer.

Abstract: A method includes receiving a substrate having a front surface and a back surface; forming an isolation feature of a first dielectric material in the substrate, thereby defining an active region surrounded by the isolation feature; forming a gate stack on the active regions; forming a first and a second S/D feature on the fin active region; forming a front contact feature contacting the first S/D feature; thinning down the substrate from the back surface such that the isolation feature is exposed; selectively etching the active region, resulting in a trench surrounded by the isolation feature, the second S/D feature being exposed within the trench; forming, in the trench, a liner layer of a second dielectric material being different from the first dielectric material; forming a backside via feature landing on the second S/D feature within the trench; and forming a backside metal line landing on the backside via feature.

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: A device includes a substrate, a gate structure over the substrate, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer, wherein a bottom surface of the dielectric liner is spaced away from the silicide by a gap, and an S/D contact over the silicide and at least partially filling the gap.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a source/drain (S/D) feature formed in an interlayer dielectric layer (ILD), a S/D contact via electrically connected to the S/D feature, a metal feature formed over the S/D contact via, and a metal line formed over the metal feature and electrically connected to the S/D contact via. The metal line is formed of a material different from that of the S/D contact via, and the S/D contact via is spaced apart from the metal line. By providing the metal feature, electromigration between the metal line and the contact via may be advantageously reduced or substantially eliminated.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.