Abstract: A composition comprising a C2-C12 polyalphaolefin and a functionalized propylene-based elastomer comprising from about 4 to about 25 wt % units derived from one or more C2 or C4-C12 alpha-olefins; a triad tacticity greater than about 90%; a heat of fusion less than about 75 J/g; and a plurality of oxygen containing functional groups selected from carboxylic acids, anhydrides, ketones, carbonates, esters, ethers, lactones, and combinations thereof. Compositions containing the functionalized propylene-based elastomer and methods to produce the same are also disclosed.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: A barrage with a function of collecting floating garbage on a water surface is provided. It includes a first dam body as a main body of the barrage provided with multiple built-in low water level drainage channels and high water level drainage channels, a second dam body provided with multiple notches for converging floating garbage on the water surface, a garbage collecting and storing equipment arranged between the first dam body and the second dam body and a solar power generating equipment. The garbage collecting and storing equipment maintains running of the garbage conveyor belt by utilizing electric energy provided by the solar power generating equipment, thereby collecting garbage in a garbage pool beside the barrage. It not only has conventional functions of the barrage, but also greatly saves cost of manually salvaging garbage and avoids water pollution caused by accumulation of garbage on the river surface.

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

Abstract: An over-current protection device comprises first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer comprises a polymer matrix and carbon black. The polymer matrix comprises a fluoropolymer having a melting point higher than 150° C. The carbon black is dispersed in the polymer matrix. A resistance jump Rjump_1000@16V/50A of the over-current protection device at 16V/50 A by 1000 cycles is 0.80-1.20. A resistance jump Rjump_1000@25V/50A of the over-current protection device at 25V/50 A by 1000 cycles is 0.90-1.30.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.

Abstract: A semiconductor device includes a first gate structure and a second gate structure over a fin, a dielectric cut pattern sandwiched by the first and second gate structures, and a liner layer surrounding the dielectric cut pattern. The dielectric cut pattern is spaced apart from the fin and extends further from the substrate than a first gate electrode of the first gate structure and a second gate electrode of the second gate structure. The semiconductor device further includes a conductive feature sandwiched by the first and second gate structures. The conductive feature is divided by the conductive feature into a first segment and a second segment. The first segment of the conductive feature is above a source/drain region of the fin.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Abstract: The present invention relates to a composite comprising (1) a bottom layer comprising expanded thermoplastic elastomer particles; and (2) a surface layer on the bottom layer, and the use of such composites in flooring surfaces sports, sports hall floorings, swimming pool hall floorings, running tracks, sports facilities, playgrounds, kindergartens, park walkway and pavements.

Abstract: The present invention relates to a method of manufacturing a coated structural component (10) for a vehicle, comprising the steps of: providing a base component (11), hot forming the base component (11) into a molded component (12), electrochemically deburring the molded component (12), and electrolytically applying a corrosion protection layer (13) to the deburred molded component (12) to produce the structural component (10). The invention further relates to an apparatus for carrying out a method according to the invention for producing a deburred and coated structural component.

Abstract: An over-current protection device comprises first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer comprises a polymer matrix, a conductive ceramic filler, a carbon-containing conductive filler, and an inner filler. The polymer matrix comprises a fluoropolymer having a melting point higher than 150° C. The inner filler is selected from one of aluminum nitride, silicon carbide, zirconium oxide, boron nitride, graphene, aluminum oxide, or any mixtures thereof, and comprises 2-10% by volume of the PTC material layer. The over-current protection device is able to mitigate negative temperature coefficient (NTC) behavior after trip of device, and achieves high hold current and high endurable power.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: An integrated circuit (IC) structure includes a transistor, a front-side interconnection structure, a backside via, and a backside interconnection structure. The transistor includes a source/drain epitaxial structure. The front-side interconnection structure is on a front-side of the transistor. The backside via is connected to the source/drain epitaxial structure of the transistor. The backside interconnection structure is connected to the backside via and includes a conductive feature, a dielectric layer, and a spacer structure. The conductive feature is connected to the backside via. The dielectric layer laterally surrounds the conductive feature. The spacer structure is between the conductive feature and the dielectric layer and has an air gap.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: An over-current protection device comprises first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer comprises a polymer matrix and carbon black. The polymer matrix comprises a fluoropolymer having a melting point higher than 150° C. The carbon black is dispersed in the polymer matrix. A resistance jump Rjump_1000@16V/50A of the over-current protection device at 16V/50 A by 1000 cycles is 0.80-1.20. A resistance jump R1000@16V/50A of the over-current protection device at 25V/50 A by 1000 cycles is 0.90-1.30.