Patents by Inventor Zhen Yu

Zhen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359303
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Cheng-Chi Chuang, Li-Zhen Yu, Yi-Hsun Chiu, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220359264
    Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 10, 2022
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20220359685
    Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen YU, Cheng-Chi CHUANG, Chih-Hao WANG, Huan-Chieh SU, Lin-Yu HUANG
  • Publication number: 20220359686
    Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220359265
    Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220352015
    Abstract: A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.
    Type: Application
    Filed: September 16, 2021
    Publication date: November 3, 2022
    Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Li-Zhen YU, Lin-Yu HUANG
  • Publication number: 20220344464
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuang CHIU, Chia-Hao CHANG, Cheng-Chi CHUANG, Chih-Hao WANG, Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Yu-Ming LIN
  • Publication number: 20220344496
    Abstract: A method provides a structure having a fin oriented lengthwise and widthwise along first and second directions respectively, an isolation structure adjacent to sidewalls of the fin, and first and second source/drain (S/D) features over the fin. The method includes forming an etch mask exposing a first portion of the fin under the first S/D feature and covering a second portion of the fin under the second S/D feature; removing the first portion of the fin, resulting in a first trench; forming a first dielectric feature in the first trench; and removing the second portion of the fin to form a second trench. The first dielectric feature and the isolation structure form first and second sidewalls of the second trench respectively. The method includes laterally etching the second sidewalls, thereby expanding the second trench along the second direction and forming a via structure in the expanded second trench.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11482595
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 25, 2022
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11482594
    Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the via.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20220336287
    Abstract: A method includes receiving a substrate having a front surface and a back surface; forming an isolation feature of a first dielectric material in the substrate, thereby defining an active region surrounded by the isolation feature; forming a gate stack on the active regions; forming a first and a second S/D feature on the fin active region; forming a front contact feature contacting the first S/D feature; thinning down the substrate from the back surface such that the isolation feature is exposed; selectively etching the active region, resulting in a trench surrounded by the isolation feature, the second S/D feature being exposed within the trench; forming, in the trench, a liner layer of a second dielectric material being different from the first dielectric material; forming a backside via feature landing on the second S/D feature within the trench; and forming a backside metal line landing on the backside via feature.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220336599
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure include a source feature disposed over a backside source contact, a drain feature disposed over a backside dielectric layer, a plurality of channel members each extending between the source feature and the drain feature, and a gate structure wrapping around each of the plurality of channel members and disposed over the backside dielectric layer. The backside source contact is spaced apart from the backside dielectric layer by a gap.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220328630
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate, a source/drain contact disposed over the substrate, a first dielectric layer disposed on the source drain contact, an etch stop layer disposed on the first dielectric layer, and a source/drain conductive layer disposed in the etch stop layer and the first dielectric layer. The structure further includes a spacer structure disposed in the etch stop layer and the first dielectric layer. The spacer structure surrounds a sidewall of the source/drain conductive layer and includes a first spacer layer having a first portion and a second spacer layer adjacent the first portion of the first spacer layer. The first portion of the first spacer layer and the second spacer layer are separated by an air gap. The structure further includes a seal layer.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventors: Lin-Yu HUANG, Li-Zhen YU, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20220319913
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a gate electrode over a substrate. The gate electrode is laterally separated from a dielectric by a spacer structure. A sacrificial layer is formed over a top surface of the gate electrode. A liner layer is formed along a sidewall of the spacer structure and on the sacrificial layer. The sacrificial layer is removed and a hard mask material is formed over the gate electrode. A part of the dielectric is removed to form a contact opening laterally separated from the gate electrode by the spacer structure. A conductive contact is formed within the contact opening.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
  • Publication number: 20220310804
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Shih-Chuan CHIU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Patent number: 11456246
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11456209
    Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11450751
    Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang
  • Publication number: 20220293521
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.
    Type: Application
    Filed: February 28, 2022
    Publication date: September 15, 2022
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220293429
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 15, 2022
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang