Patents by Inventor Zheng Bo
Zheng Bo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446563Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.Type: GrantFiled: April 4, 2018Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, John H. Macpeak, Douglas T. Grider
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Publication number: 20190312045Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: Xiang-Zheng BO, John H. MACPEAK, Douglas T. GRIDER
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Publication number: 20190207025Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.Type: ApplicationFiled: January 15, 2018Publication date: July 4, 2019Inventors: Xiang-Zheng BO, Michelle N. NGUYEN, Douglas T. GRIDER
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Patent number: 9431248Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: GrantFiled: October 2, 2015Date of Patent: August 30, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Patent number: 9397164Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: GrantFiled: November 18, 2015Date of Patent: July 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Patent number: 9344105Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.Type: GrantFiled: May 5, 2014Date of Patent: May 17, 2016Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTEInventors: Ting Li, Ru-Zhang Li, Yong Zhang, Zheng-Bo Huang, Guang-Bing Chen, Jian-An Wang, Yu-Xin Wang, Dong-Bing Fu, Yan Wang, Xu Wang
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Publication number: 20160112059Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.Type: ApplicationFiled: May 5, 2014Publication date: April 21, 2016Inventors: TING LI, RU-ZHANG LI, YONG ZHANG, ZHENG-BO HUANG, GUANG-BING CHEN, JIAN-AN WANG, YU-XIN WANG, DONG-BING FU, YAN WANG, XU WANG
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Publication number: 20160079364Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: ApplicationFiled: November 18, 2015Publication date: March 17, 2016Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Publication number: 20160027647Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Patent number: 9245755Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: GrantFiled: December 18, 2014Date of Patent: January 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Patent number: 9187823Abstract: A method of growing carbon nanostructures on a conductive substrate without the need for a vacuum or low-pressure environment provides high electrical field strengths to generate the necessary carbon ions from a feedstock gas and to promote alignment and separation of the resulting structures. In one embodiment, substantially uniform “vertical” nanostructures may be formed around the periphery of an extended wire for use in corona discharge applications or the like. Growth on a planar substrate may provide use with a variety of apparatus requiring a high specific surface conductor such as capacitors, batteries, and solar cells.Type: GrantFiled: September 7, 2012Date of Patent: November 17, 2015Assignee: National Science FoundationInventors: Junhong Chen, Kehan Yu, Zheng Bo, Guahua Lu
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Patent number: 9177802Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: GrantFiled: December 27, 2013Date of Patent: November 3, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Publication number: 20150240351Abstract: A method of growing carbon nanostructures on a conductive substrate without the need for a vacuum or low-pressure environment provides high electrical field strengths to generate the necessary carbon ions from a feedstock gas and to promote alignment and separation of the resulting structures. In one embodiment, substantially uniform “vertical” nanostructures may be formed around the periphery of an extended wire for use in corona discharge applications or the like. Growth on a planar substrate may provide use with a variety of apparatus requiring a high specific surface conductor such as capacitors, batteries, and solar cells.Type: ApplicationFiled: September 7, 2012Publication date: August 27, 2015Inventors: Junhong Chen, Kehan Yu, Zheng Bo, Guahua Lu
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Publication number: 20150187760Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.Type: ApplicationFiled: December 18, 2014Publication date: July 2, 2015Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
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Publication number: 20140187008Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: ApplicationFiled: December 27, 2013Publication date: July 3, 2014Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Patent number: 8767583Abstract: A network resource allocating method for a residential gateway includes the following steps. A first downlink bandwidth is allocated to a residential gateway for process of a first service. A second downlink bandwidth is allocated to the residential gateway for process of a second service. A processing priority of the first service is higher than a processing priority of the second service. A first downlink rate of the residential gateway is detected when the residential gateway processes the first service. A second downlink rate of the residential gateway is detected when the residential gateway processes the second service. A bandwidth usage state of the residential gateway is determined according to the first and the second downlink rates. The second downlink bandwidth of the residential gateway is adjusted according to the bandwidth usage state such that the quality of service (QoS) of the first service or the second service is enhanced.Type: GrantFiled: August 31, 2011Date of Patent: July 1, 2014Assignee: Sercomm CorporationInventors: Zheng-Bo Zhou, Ruo-Yu Cao
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Publication number: 20130039175Abstract: A bandwidth control method is provided. A router is provided to establish a network connection to a remote apparatus. The remote apparatus is allocated with a downlink bandwidth for servicing the gateway. A plurality of downlink packets are received by the gateway. In response to reception of the downlink packets, the gateway transmits a plurality of uplink packets to the remote apparatus to allow the remote apparatus to transmit more downlink packets to the gateway after the remote apparatus acknowledges reception of the uplink packets. A transmission rate of the uplink packets is limited within an uplink threshold by the gateway so that a transmission rate of the downlink packets is smaller than the downlink bandwidth allocated to the remote apparatus. The uplink threshold is determined based on the downlink bandwidth.Type: ApplicationFiled: July 19, 2012Publication date: February 14, 2013Applicant: SERNET (SUZHOU) TECHNOLOGIES CORPORATIONInventors: Zheng-Bo Zhou, Ruo-Yu Cao
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Publication number: 20120287816Abstract: A network resource allocating method for a residential gateway includes the following steps. A first downlink bandwidth is allocated to a residential gateway for process of a first service. A second downlink bandwidth is allocated to the residential gateway for process of a second service. A processing priority of the first service is higher than a processing priority of the second service. A first downlink rate of the residential gateway is detected when the residential gateway processes the first service. A second downlink rate of the residential gateway is detected when the residential gateway processes the second service. A bandwidth usage state of the residential gateway is determined according to the first and the second downlink rates. The second downlink bandwidth of the residential gateway is adjusted according to the bandwidth usage state such that the quality of service (QoS) of the first service or the second service is enhanced.Type: ApplicationFiled: August 31, 2011Publication date: November 15, 2012Applicant: SERCOMM CORPORATIONInventors: Zheng-Bo Zhou, Ruo-Yu Cao
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Publication number: 20110210401Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
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Patent number: 7700499Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.Type: GrantFiled: January 11, 2008Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo