Patents by Inventor Zheng Bo

Zheng Bo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446563
    Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiang-Zheng Bo, John H. Macpeak, Douglas T. Grider
  • Publication number: 20190312045
    Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Xiang-Zheng BO, John H. MACPEAK, Douglas T. GRIDER
  • Publication number: 20190207025
    Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.
    Type: Application
    Filed: January 15, 2018
    Publication date: July 4, 2019
    Inventors: Xiang-Zheng BO, Michelle N. NGUYEN, Douglas T. GRIDER
  • Patent number: 9431248
    Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
  • Patent number: 9397164
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Patent number: 9344105
    Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 17, 2016
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Ting Li, Ru-Zhang Li, Yong Zhang, Zheng-Bo Huang, Guang-Bing Chen, Jian-An Wang, Yu-Xin Wang, Dong-Bing Fu, Yan Wang, Xu Wang
  • Publication number: 20160112059
    Abstract: A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.
    Type: Application
    Filed: May 5, 2014
    Publication date: April 21, 2016
    Inventors: TING LI, RU-ZHANG LI, YONG ZHANG, ZHENG-BO HUANG, GUANG-BING CHEN, JIAN-AN WANG, YU-XIN WANG, DONG-BING FU, YAN WANG, XU WANG
  • Publication number: 20160079364
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 17, 2016
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Publication number: 20160027647
    Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.
    Type: Application
    Filed: October 2, 2015
    Publication date: January 28, 2016
    Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
  • Patent number: 9245755
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Patent number: 9187823
    Abstract: A method of growing carbon nanostructures on a conductive substrate without the need for a vacuum or low-pressure environment provides high electrical field strengths to generate the necessary carbon ions from a feedstock gas and to promote alignment and separation of the resulting structures. In one embodiment, substantially uniform “vertical” nanostructures may be formed around the periphery of an extended wire for use in corona discharge applications or the like. Growth on a planar substrate may provide use with a variety of apparatus requiring a high specific surface conductor such as capacitors, batteries, and solar cells.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 17, 2015
    Assignee: National Science Foundation
    Inventors: Junhong Chen, Kehan Yu, Zheng Bo, Guahua Lu
  • Patent number: 9177802
    Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 3, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
  • Publication number: 20150240351
    Abstract: A method of growing carbon nanostructures on a conductive substrate without the need for a vacuum or low-pressure environment provides high electrical field strengths to generate the necessary carbon ions from a feedstock gas and to promote alignment and separation of the resulting structures. In one embodiment, substantially uniform “vertical” nanostructures may be formed around the periphery of an extended wire for use in corona discharge applications or the like. Growth on a planar substrate may provide use with a variety of apparatus requiring a high specific surface conductor such as capacitors, batteries, and solar cells.
    Type: Application
    Filed: September 7, 2012
    Publication date: August 27, 2015
    Inventors: Junhong Chen, Kehan Yu, Zheng Bo, Guahua Lu
  • Publication number: 20150187760
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Application
    Filed: December 18, 2014
    Publication date: July 2, 2015
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Publication number: 20140187008
    Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
  • Patent number: 8767583
    Abstract: A network resource allocating method for a residential gateway includes the following steps. A first downlink bandwidth is allocated to a residential gateway for process of a first service. A second downlink bandwidth is allocated to the residential gateway for process of a second service. A processing priority of the first service is higher than a processing priority of the second service. A first downlink rate of the residential gateway is detected when the residential gateway processes the first service. A second downlink rate of the residential gateway is detected when the residential gateway processes the second service. A bandwidth usage state of the residential gateway is determined according to the first and the second downlink rates. The second downlink bandwidth of the residential gateway is adjusted according to the bandwidth usage state such that the quality of service (QoS) of the first service or the second service is enhanced.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: July 1, 2014
    Assignee: Sercomm Corporation
    Inventors: Zheng-Bo Zhou, Ruo-Yu Cao
  • Publication number: 20130039175
    Abstract: A bandwidth control method is provided. A router is provided to establish a network connection to a remote apparatus. The remote apparatus is allocated with a downlink bandwidth for servicing the gateway. A plurality of downlink packets are received by the gateway. In response to reception of the downlink packets, the gateway transmits a plurality of uplink packets to the remote apparatus to allow the remote apparatus to transmit more downlink packets to the gateway after the remote apparatus acknowledges reception of the uplink packets. A transmission rate of the uplink packets is limited within an uplink threshold by the gateway so that a transmission rate of the downlink packets is smaller than the downlink bandwidth allocated to the remote apparatus. The uplink threshold is determined based on the downlink bandwidth.
    Type: Application
    Filed: July 19, 2012
    Publication date: February 14, 2013
    Applicant: SERNET (SUZHOU) TECHNOLOGIES CORPORATION
    Inventors: Zheng-Bo Zhou, Ruo-Yu Cao
  • Publication number: 20120287816
    Abstract: A network resource allocating method for a residential gateway includes the following steps. A first downlink bandwidth is allocated to a residential gateway for process of a first service. A second downlink bandwidth is allocated to the residential gateway for process of a second service. A processing priority of the first service is higher than a processing priority of the second service. A first downlink rate of the residential gateway is detected when the residential gateway processes the first service. A second downlink rate of the residential gateway is detected when the residential gateway processes the second service. A bandwidth usage state of the residential gateway is determined according to the first and the second downlink rates. The second downlink bandwidth of the residential gateway is adjusted according to the bandwidth usage state such that the quality of service (QoS) of the first service or the second service is enhanced.
    Type: Application
    Filed: August 31, 2011
    Publication date: November 15, 2012
    Applicant: SERCOMM CORPORATION
    Inventors: Zheng-Bo Zhou, Ruo-Yu Cao
  • Publication number: 20110210401
    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
  • Patent number: 7700499
    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo