Abstract: A brush phase shifter includes an actuating member, a gear assembly, a main printed circuit board and a brush member. The gear assembly includes a driving gear, a transmission gear and a linkage gear. The driving gear is a bevel gear. The transmission gear includes a bevel gear portion and a cylindrical gear portion. The bevel gear portion has a large end and a small end. The cylindrical gear portion is integrally formed at the large end of the bevel gear portion. The linkage gear is a cylindrical gear. The driving gear meshes with the bevel gear portion of the transmission gear. The cylindrical gear portion of the transmission gear meshes with the linkage gear. The brush member is fixedly connected with the linkage gear. The brush member is rotatably arranged on the main printed circuit board. The present disclosure precisely controls the phase change and realize miniaturization.

Abstract: The present invention relates to the field of immunology. More specifically, the present invention provides methods and compositions directed to the use of antibodies to the pancreatic zinc transporter, ZnT8. In particular embodiments, the anti-ZnT8 antibodies specifically bind the transmembrane domain of ZnT8. In more specific embodiments, the anti-ZnT8 antibodies specifically the extracellular surface of the transmembrane domain.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: The present embodiments relate to systems and methods for automatic sign in upon account signup. Particularly, the present embodiments can utilize a federated login approach for automatic sign in upon account signup for a cloud infrastructure. Specifically, the signup and sign in service (also known as SOUP) and an identity provider portal can be configured such that the nodes are aware of each other as Security Assertion Markup Language (SAML) partners. After new account registration, the signup service can redirect the user browser to a cloud infrastructure console to start with a federated login flow, where a sign in service can issue a SAML authentication request, and redirects it to signup service. Responsive to validating the browser using a SAML authentication process, the browser can be automatically signed into the new account and allowed access the account relating to the cloud infrastructure service.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: A system including a processor and non-transitory computer-readable media storing computing instructions that, when executed on the processor, perform a method that includes training a machine learning model by using a training data set to determine taxonomy embeddings for taxonomies based on training features that include a context word vector, a center word vector, and a probability. The probability corresponds to a function between the context word vector and the center word vector. The taxonomy embeddings represent at least a first level of a taxonomy and a second level of the taxonomy. The machine learning model, as trained, is used to determine the taxonomy embeddings based on taxonomy identifiers and reduce the taxonomy embeddings by removing at least one taxonomy of the taxonomies that are below a threshold to thereby reduce the taxonomies. The threshold comprises a number of aggregate page views.

Abstract: An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.

Abstract: The disclosure provides methods for the long-term expansion of granulocyte-macrophage progenitors, the granulocyte-macrophage progenitors generated therefrom, and uses of the granulocyte-macrophage progenitors thereof.

Abstract: A system including one or more processors and one or more non-transitory computer readable media storing computing instructions that, when executed on the one or more processors, perform: receiving a taxonomy identifier corresponding to a taxonomy for a product; determining taxonomy embeddings based on the taxonomy identifier, the taxonomy embeddings representing at least a first level of the taxonomy and a second level of the taxonomy; modifying taxonomies based on a threshold to reduce a number of the taxonomy embeddings in subsequent processing; and mapping the taxonomies, as modified, to publisher placements to display the product within the taxonomies on a graphical user interface (GUI).

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: The present embodiments relate to systems and methods for automatic sign in upon account signup. Particularly, the present embodiments can utilize a federated login approach for automatic sign in upon account signup for a cloud infrastructure. Specifically, the signup and sign in service (also known as SOUP) and an identity provider portal can be configured such that the nodes are aware of each other as Security Assertion Markup Language (SAML) partners. After new account registration, the signup service can redirect the user browser to a cloud infrastructure console to start with a federated login flow, where a sign in service can issue a SAML authentication request, and redirects it to signup service. Responsive to validating the browser using a SAML authentication process, the browser can be automatically signed into the new account and allowed access the account relating to the cloud infrastructure service.

Abstract: A brush phase shifter includes an actuating member, a gear assembly, a main printed circuit board and a brush member. The gear assembly includes a driving gear, a transmission gear and a linkage gear. The driving gear is a bevel gear. The transmission gear includes a bevel gear portion and a cylindrical gear portion. The bevel gear portion has a large end and a small end. The cylindrical gear portion is integrally formed at the large end of the bevel gear portion. The linkage gear is a cylindrical gear. The driving gear meshes with the bevel gear portion of the transmission gear. The cylindrical gear portion of the transmission gear meshes with the linkage gear. The brush member is fixedly connected with the linkage gear. The brush member is rotatably arranged on the main printed circuit board. The present disclosure precisely controls the phase change and realize miniaturization.

Abstract: The present embodiments relate to systems and methods for automatic sign in upon account signup. Particularly, the present embodiments can utilize a federated login approach for automatic sign in upon account signup for a cloud infrastructure. Specifically, the signup and sign in service (also known as SOUP) and an identity provider portal can be configured such that the nodes are aware of each other as Security Assertion Markup Language (SAML) partners. After new account registration, the signup service can redirect the user browser to a cloud infrastructure console to start with a federated login flow, where a sign in service can issue a SAML authentication request, and redirects it to signup service. Responsive to validating the browser using a SAML authentication process, the browser can be automatically signed into the new account and allowed access the account relating to the cloud infrastructure service.

Abstract: Disclosed are an online analysis system and method for a line loss of a transmission line. The system includes: a terminal extension and a terminal host, where time information synchronization between the terminal extension and the terminal host and between terminal extensions is performed by a clock synchronization module, and communication between the terminal extension and the terminal host and between the terminal extensions is performed by a communications module; and a line loss management platform, configured to receive measurement data of the terminal extension and the terminal host, match time information in the measurement data, and if time information in the measurement data of the terminal extension and the terminal host is matched, and time information in measurement data of the terminal extensions is matched, determine corresponding line loss information based on corresponding measurement information.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.