Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: A system including one or more processors and one or more non-transitory computer readable media storing computing instructions that, when executed on the one or more processors, perform: receiving a taxonomy identifier corresponding to a taxonomy for a product; determining taxonomy embeddings based on the taxonomy identifier, the taxonomy embeddings representing at least a first level of the taxonomy and a second level of the taxonomy; modifying taxonomies based on a threshold to reduce a number of the taxonomy embeddings in subsequent processing; and mapping the taxonomies, as modified, to publisher placements to display the product within the taxonomies on a graphical user interface (GUI).

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

Abstract: Disclosed are a benzonitric heterocyclic compound, a preparation method therefor and the use thereof. Provided in the present invention is a benzonitric heterocyclic compound represented by formula I, or a pharmaceutically acceptable salt thereof, which can be used as a histone deacetylase inhibitor, has a selective inhibitory effect on HDAC6, and has characteristics such as a high efficiency, low toxicity and ideal pharmacokinetic properties.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: An antenna oscillator unit includes a radiator and a balun support. The radiator is fixed to the balun support and includes a plurality of low-frequency oscillator arms circumferentially distributed along the balun support. Each of the low-frequency oscillator arms includes two radiating sections connected to each other and a connecting section connecting the two radiating sections to form a closed loop. The two radiating sections are substantially perpendicular to each other. The antenna oscillator unit of some embodiments can avoid mutual coupling of signals from the antenna oscillator unit and an adjacent high-frequency oscillator and can improve the capability to radiate electromagnetic signals.

Abstract: Disclosed are an online analysis system and method for a line loss of a transmission line. The system includes: a terminal extension and a terminal host, where time information synchronization between the terminal extension and the terminal host and between terminal extensions is performed by a clock synchronization module, and communication between the terminal extension and the terminal host and between the terminal extensions is performed by a communications module; and a line loss management platform, configured to receive measurement data of the terminal extension and the terminal host, match time information in the measurement data, and if time information in the measurement data of the terminal extension and the terminal host is matched, and time information in measurement data of the terminal extensions is matched, determine corresponding line loss information based on corresponding measurement information.

Abstract: The present embodiments relate to systems and methods for automatic sign in upon account signup. Particularly, the present embodiments can utilize a federated login approach for automatic sign in upon account signup for a cloud infrastructure. Specifically, the signup and sign in service (also known as SOUP) and an identity provider portal can be configured such that the nodes are aware of each other as Security Assertion Markup Language (SAML) partners. After new account registration, the signup service can redirect the user browser to a cloud infrastructure console to start with a federated login flow, where a sign in service can issue a SAML authentication request, and redirects it to signup service. Responsive to validating the browser using a SAML authentication process, the browser can be automatically signed into the new account and allowed access the account relating to the cloud infrastructure service.

Abstract: The present invention is directed to a method for improving the occlusiveness of a topical pharmaceutical or cosmetic formulation in use in a patient in need thereof, comprising adding to the formulation at least 0.1- to about 10% w/w of one or more of a monofatty acid ester of glycerin and/or one or more of a monofatty acid ester of glycol, or mixtures thereof. The present invention is also directed to a method for maintaining skin barrier efficiency of the stratum corneum of a patient in need thereof, comprising applying to the skin of said patient a pharmaceutical or cosmetic formulation containing at least 3% w/w of one or more of a monofatty acid ester of glycerin and/or one or more of a monofatty acid ester of glycol, or mixtures thereof.

Abstract: Aspects of the present invention are directed to a method for improving the occlusiveness of a topical pharmaceutical or cosmetic formulation in use in a patient in need thereof, comprising adding to the formulation at least 0.1-to about 10% w/w of one or more of a monofatty acid ester of glycerin and/or one or more of a monofatty acid ester of glycol, or mixtures thereof. Aspects of the present invention are also directed to a method for maintaining skin barrier efficiency of the stratum corneum of a patient in need thereof, comprising applying to the skin of said patient a pharmaceutical or cosmetic formulation containing at least 3% w/w of one or more of a monofatty acid ester of glycerin and/or one or more of a monofatty acid ester of glycol, or mixtures thereof.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

Abstract: An antenna oscillator unit includes a radiator and a balun support. The radiator is fixed to the balun support and includes a plurality of low-frequency oscillator arms circumferentially distributed along the balun support. Each of the low-frequency oscillator arms includes two radiating sections connected to each other and a connecting section connecting the two radiating sections to form a closed loop. The two radiating sections are substantially perpendicular to each other. The antenna oscillator unit of some embodiments can avoid mutual coupling of signals from the antenna oscillator unit and an adjacent high-frequency oscillator and can improve the capability to radiate electromagnetic signals.