Abstract: A method of a polyurethane foam includes the following steps of: (1) simultaneously pumping a mixed solution prepared from hydrogen peroxide, an organic acid, a catalyst and a stabilizer and a vegetable oil into a first microstructured reactor of a micro-channel modular reaction device for reacting to obtain a reaction solution containing epoxidized vegetable oil; (2) simultaneously pumping the reaction solution containing the epoxidized vegetable oil obtained from the step (1) and a compound of formula III into a second microstructured reactor of the micro-channel modular reaction device for reaction to obtain a vegetable oil polyol; and (3) reacting the vegetable oil polyol prepared from the step (2) with a foam stabilizer, a cyclohexylamine, an isocyanate and a foaming agent cyclopentane for foaming so as to prepare a rigid polyurethane foam.

Abstract: A preparation method of a flexible polyurethane foam includes the following steps of: (1) subjecting an epoxidized vegetable oil, a benzoylformic acid, a basic catalyst, and an inert solvent to a ring-opening reaction in a first microchannel reactor of a microchannel reaction device to obtain a vegetable oil polyol; (2) subjecting the vegetable oil polyol obtained in the step (1), a propylene oxide and an inert solvent to an addition polymerization reaction in a second microchannel reactor of the microchannel reaction device to obtain a vegetable oil polyol for flexible polyurethane foam; and (3) using the vegetable oil polyol for flexible polyurethane foam obtained in the step (2) as the unique polyol, and subjecting the same and an isocyanate polyol to a foaming reaction to obtain the flexible polyurethane foam.

Abstract: A method is provided for forming an interconnect structure for an integrated circuit.

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

Abstract: A method is provided for forming a semiconductor product including providing a substrate comprising a buried power rail; forming a sacrificial plug at a contact surface on the buried power rail; applying a front-end-of-line module for forming devices in the semiconductor substrate; providing a Via, through layers applied by the front-end-module, which joins the sacrificial plug on the buried power rail; selectively removing the sacrificial plug thereby obtaining a cavity above the buried power rail; filling the cavity with a metal to electrically connect the devices with the buried power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than an area of a cross-section of the Via parallel with the contact surface.

Abstract: Methods and compositions containing a phorbol ester or a derivative of a phorbol ester are provided for the treatment of chronic and acute conditions. Such conditions may be caused by disease, be symptoms or sequelae of disease. Chronic and acute conditions may be due to viral infections such as HIV and AIDS, neoplastic diseases stroke, kidney disease, urinary incontinence, autoimmune disorders, Parkinson's disease, prostate hypertrophy, aging, dementia, or the treatment of such diseases. Additional compositions and methods are provided which employ a phorbol ester or derivative compound in combination with at least one additional agent to yield more effective treatment tools against acute and chronic conditions in mammalian subjects.

Abstract: Methods and compositions containing a phorbol ester or a derivative of a phorbol ester are provided for the treatment of chronic and acute conditions. Such conditions may be caused by disease, be symptoms or sequelae of disease. Chronic and acute conditions may be due to viral infections such as HIV and AIDS, neoplastic diseases stroke, kidney disease, urinary incontinence, autoimmune disorders, Parkinson's disease, prostate hypertrophy, aging, or the treatment of such diseases. Additional compositions and methods are provided which employ a phorbol ester or derivative compound in combination with at least one additional agent to yield more effective treatment tools against acute and chronic conditions in mammalian subjects.

Abstract: A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

Abstract: A method for forming an interconnection structure (10) for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines (113) above a first and second conductive line (101, 108). At least one of the third conductive lines comprises a contacting portion forming a first via connection (114) to the second conductive line. The method further comprises forming spacers (115) on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole (116) extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection (118) and forming a set of fourth conductive lines (119) extending between the spacers.

Abstract: A method for forming an interconnection structure for a semiconductor device and an interconnection structure is disclosed. The method includes forming a conductive layer on an insulating layer and etching the conductive layer to form a first conductive line. Thereafter, a spacer is formed on a side wall of a first end portion of the first conductive line. The method further includes forming a second conductive line, parallel to the first conductive line, having a second end portion, wherein a side wall of the second end portion is arranged to abut the spacer such that the first and the second metal line are extending along the same line and separated by the spacer. A recess is formed in the second metal line, extending along a portion of the second metal line, and a second mask layer is arranged in the recess.

Abstract: A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

Abstract: Methods and compositions containing a phorbol ester or a derivative of a phorbol ester are provided for the treatment of chronic and acute conditions. Such conditions may be caused by disease, be symptoms or sequelae of disease. Chronic and acute conditions may be due to viral infections such as HIV and AIDS, neoplastic diseases stroke, kidney disease, urinary incontinence, autoimmune disorders, Parkinson's disease, prostate hypertrophy, aging, or the treatment of such diseases. Additional compositions and methods are provided which employ a phorbol ester or derivative compound in combination with at least one additional agent to yield more effective treatment tools against acute and chronic conditions in mammalian subjects.

Abstract: Methods and compositions containing a phorbol ester or a derivative of a phorbol ester are provided for the treatment of chronic and acute conditions. Such conditions may be caused by disease, be symptoms or sequelae of disease. Chronic and acute conditions may be due to viral infections such as HIV and AIDS, neoplastic diseases stroke, kidney disease, urinary incontinence, autoimmune disorders, Parkinson's disease, prostate hypertrophy, aging, or the treatment of such diseases. Additional compositions and methods are provided which employ a phorbol ester or derivative compound in combination with at least one additional agent to yield more effective treatment tools against acute and chronic conditions in mammalian subjects.

Abstract: A method for forming a mask layer above a semiconductor fin structure is disclosed. In one aspect the method includes forming a first set of spacers and a second set of spacers arranged at the side surfaces of the first set of spacers, providing a first filler material between the second set of spacers, etching a top portion of the first filler material to form recesses between the second set of spacers, and providing a second filler material in the recesses, the second filler material forming a set of sacrificial mask lines. Further, the method includes recessing a top portion of at least the first set of spacers, providing a mask layer material between the sacrificial mask lines, and removing the sacrificial mask lines and the first filler material.

Abstract: An electric steering system (1) including a steering device (40), an actuating device (30) and a related method for controlling the electric steering system. The steering device (40) is configured to transmit steering signals in response to user operations. The actuating device (30) is configured to control the electric motor (301) to rotate a link arm (202) according to the steering signal, bringing the rotatable assembly (203) to rotate along an axis of the ship propulsion apparatus (20), thereby adjusting an orientation of the propeller (2034). The actuating device (30) is rotatably coupled to an end of the link arm (202).

Abstract: A method is provided for forming a semiconductor product including providing a substrate comprising a buried power rail; forming a sacrificial plug at a contact surface on the buried power rail; applying a front-end-of-line module for forming devices in the semiconductor substrate; providing a Via, through layers applied by the front-end-module, which joins the sacrificial plug on the buried power rail; selectively removing the sacrificial plug thereby obtaining a cavity above the buried power rail; filling the cavity with a metal to electrically connect the devices with the buried power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than an area of a cross-section of the Via parallel with the contact surface.

Abstract: Methods and compositions containing a phorbol ester or a derivative of a phorbol ester in combination with G-CSF or in combination with EPO, are provided for the treatment of cytopenia in mammalian subjects. The compositions and methods also reduce the duration of cytopenia such as neutropenia, thrombocytopenia, and/or anemia.

Abstract: Methods and compositions containing a phorbol ester or a derivative of a phorbol ester in combination with G-CSF or in combination with EPO, are provided for the treatment of cytopenia in mammalian subjects. The compositions and methods also reduce the duration of cytopenia such as neutropenia, thrombocytopenia, and/or anemia.