Patents by Inventor Zhenxing Bi

Zhenxing Bi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190140053
    Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Zheng Xu
  • Publication number: 20190139764
    Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 9, 2019
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Publication number: 20190140064
    Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.
    Type: Application
    Filed: October 14, 2018
    Publication date: May 9, 2019
    Inventors: Zhenxing Bi, Kangguo Cheng, Heng Wu, Peng Xu
  • Patent number: 10283592
    Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10276452
    Abstract: A method of forming a semiconductor structure includes forming first and second stacked nanosheet channel structures on a semiconductor substrate, with each nanosheet channel structure including a plurality of stacked channel regions interspersed with sacrificial regions. In a resulting semiconductor structure, an N-type stacked nanosheet channel structure is formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure is formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures includes a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Romain J. Lallement, Ruqiang Bao, Zhenxing Bi, Sivananda Kanakasabapathy
  • Publication number: 20190122574
    Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 25, 2019
    Inventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Krishna R. Tunga, Loma Vaishnav
  • Publication number: 20190115263
    Abstract: Methods are provided for fabricating semiconductor fins having uniform profiles. For example, a method includes forming semiconductor fins on a substrate, including a first semiconductor fin disposed in a first device region, and a second semiconductor fin disposed in a second device region. The first and second semiconductor fins are formed of different types of semiconductor material, and are initially formed to have different widths and heights. A semiconductor fin trimming process is performed, which is selective to the semiconductor material of the second semiconductor fin, so that the fin trimming process results in the formation of semiconductor fins having substantially equal heights and equal widths across the device regions as a result of the fin trimming process. The semiconductor fins in different device regions are initially formed with non-uniform profiles (e.g., differential heights and widths) to compensate for micro-loading and etch rate variations during the fin trimming process.
    Type: Application
    Filed: June 26, 2018
    Publication date: April 18, 2019
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10263100
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device. The fabrication operations include forming a sacrificial nanosheet and a channel nanosheet over a substrate, forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet, wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10262861
    Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10263075
    Abstract: Methods of forming integrated chips include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10249755
    Abstract: An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Heng Wu, Zhenxing Bi
  • Publication number: 20190096669
    Abstract: A method for forming a nanosheet semiconductor device includes forming a nanosheet stack comprising channel nanosheets. The method includes depositing silicon on the nanosheet stack, the silicon completely filling a space between adjacent channel nanosheets. The method includes etching the silicon. The method includes exposing the nanosheet stack to a gas phase heat treatment.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Nicolas J. Loubet, Binglin Miao, Muthumanickam Sankarapandian, Charan V. Surisetty, Chun W. Yeung, Jingyun Zhang
  • Patent number: 10242882
    Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sean Teehan
  • Patent number: 10236290
    Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10236346
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example method includes forming a fin channel over a bottom source-or-drain (S/D) region, wherein the fin channel includes an upper fin channel region and a lower fin channel region, and wherein the bottom S/D region includes an upper S/D region and a lower S/D region. The method further includes forming a S/D junction at an interface between the lower fin channel region and the upper S/D region. A doping process is applied. The doping process is configured to drive a first type of dopant into the upper fin channel region.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Chen Zhang
  • Patent number: 10236364
    Abstract: A tunnel field-effect transistor having source and drain contacts made from different electrically conductive materials enables independent optimization of contact resistance on the source and drain sides of the transistor. Dielectric caps on the gate electrode, source contact and drain contact made from different materials allow the selective removal of portions of the caps during gate, source and drain wiring. A wiring strap can be formed across the gate and drain to electrically connect two source contacts together. Multiple drain contacts or multiple gate electrodes may alternatively be electrically connected by wiring straps. Strap wiring facilitates placing transistors in closer proximity to increase the number of transistors for a given chip area.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 19, 2019
    Assignee: International Busines Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Heng Wu, Zhenxing Bi
  • Patent number: 10217707
    Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10217658
    Abstract: A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions are on a top surface of the liner layer on the substrate and includes a dielectric layer; and a doped region on the dielectric layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Hao Tang
  • Patent number: 10211288
    Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Zheng Xu
  • Publication number: 20190051535
    Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: October 15, 2018
    Publication date: February 14, 2019
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Xin Miao