Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate real-time response to defined symptoms are provided. In one embodiment, a computer-implemented method comprises: monitoring, by a system operatively coupled to a processor, a state of an entity; detecting, by the system, defined symptoms of the entity by analyzing the state of the entity; and transmitting, by the system, a signal that causes audio response or a haptic response to be provided to the entity, wherein transmission of the signal that causes the audio response or the haptic response is based on detection of the defined symptoms.

Abstract: Embodiments of the invention are directed to a field effect transistor (FET) device including a first channel region over a first region of a substrate; a second channel region over a second region of the substrate and adjacent to the first channel region; and a bottom conductive layer over a third region of the substrate and operable to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact. The first region of the substrate, the second region of the substrate, and the third region of the substrate do not overlap. The bottom conductive layer includes a non-uniform height having a first section and a second section. The first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region.

Abstract: Stacked nanosheet complementary metal-oxide-semiconductor field effect transistor devices include a lower semiconductor channel sheet on a substrate. An upper semiconductor channel sheet is on the substrate above the lower semiconductor channel sheet. The upper semiconductor channel sheet is a different semiconductor material than the lower semiconductor channel sheet. A dielectric substitute partition sheet is on the substrate between the upper semiconductor channel sheet and the lower semiconductor channel sheet.

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a field effect transistor (FET) device on a substrate. The fabrication operations include forming a channel region over the substrate, forming a bottom conductive layer of a wrap-around source or drain (S/D) contact over the substrate, and forming a S/D region over the bottom conductive layer and adjacent to the channel region. The S/D region is communicatively coupled to the channel region and the bottom conductive layer.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

Abstract: Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

Abstract: A method for fabricating a stacked nanopore includes forming a stack of layers having alternating conductive lines and dielectric layers on a substrate, and patterning the stack to form a staircase structure with the conductive lines having a length gradually changing at each level in the stack. The method also includes depositing and planarizing a dielectric material over the staircase structure, forming contacts through the dielectric material to the conductive lines for each level of conductive lines, etching a nanopore through the stack of layers to form pairs of opposing electrodes across the nanopore using the conductive lines; and opening up the substrate to expose the nanopore.

Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.

Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning. Responsive to the individual being a baby, the voice-to-language processor discretizes baby babbling to consonants, letters, and words.

Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Abstract: Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate real-time response to defined symptoms are provided. In one embodiment, a computer-implemented method comprises: monitoring, by a system operatively coupled to a processor, a state of an entity; detecting, by the system, defined symptoms of the entity by analyzing the state of the entity; and transmitting, by the system, a signal that causes audio response or a haptic response to be provided to the entity, wherein transmission of the signal that causes the audio response or the haptic response is based on detection of the defined symptoms.

Abstract: A computer system interacts with a user with a behavioral state. An activity performed by an entity with a behavioral state is determined. A virtual character corresponding to the entity and performing the determined activity of the entity is generated and displayed. A mental state of the entity responsive to the virtual character is detected. In response to detection of a positive mental state of the entity, one or more natural language terms are provided to the entity corresponding to the activity performed by the virtual character. Embodiments of the present invention further include a method and program product for interacting with a user with a behavioral state in substantially the same manner described above.