Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: A semiconductor structure is provided that includes a gate conductor structure having a middle portion that has a vertical thickness that is greater than a vertical thickness of each end portion, and a self-aligned dielectric gate cap located on the gate conductor structure and having a middle portion that has a vertical thickness that is less than a vertical thickness of each end portion. The aforementioned gate conductor structure, which is taller in the middle and shorter at the edges, has reduced gate resistance, while the aforementioned self-aligned dielectric gate cap, which is taller at the edges and shorter in the middle, increases process margin for contact formation.

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate real-time response to defined symptoms are provided. In one embodiment, a computer-implemented method comprises: monitoring, by a system operatively coupled to a processor, a state of an entity; detecting, by the system, defined symptoms of the entity by analyzing the state of the entity; and transmitting, by the system, a signal that causes audio response or a haptic response to be provided to the entity, wherein transmission of the signal that causes the audio response or the haptic response is based on detection of the defined symptoms.

Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.

Abstract: Provided are embodiments of a method for forming a semiconductor device. The method includes forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises channel layers and nanosheet layers, forming a sacrificial gate over the nanosheet stack, and forming trenches to expose sidewalls of the nanosheet stack. The method also includes forming source/drain (S/D) regions, where forming the S/D regions including forming first portions of the S/D regions on portions of the nano sheet stack, forming second portions of the S/D regions, wherein the first portions are different than the second portions, and replacing the sacrificial gate with a conductive gate material. Also provided are embodiments of a semiconductor device formed by the method described herein.

Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

Abstract: Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.

Abstract: A method of forming a stacked nanosheet complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device is provided. The method includes forming a plurality of semiconductor layers on a substrate, and patterning the plurality of semiconductor layers to form a plurality of multi-layer nanosheet fins with a fill layer between the multi-layer nanosheet fins and an endwall support on opposite ends of the nanosheet fins. The method further includes reducing the height of the fill layer to expose at least a top three semiconductor nanosheet segments of the multi-layer nanosheet fins, and removing two of the at least top three semiconductor nanosheet segments. The method further includes forming a protective layer on one of the at least top three semiconductor nanosheet segments.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: Provided are embodiments of a method for forming a semiconductor device. The method includes forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises channel layers and nanosheet layers, forming a sacrificial gate over the nanosheet stack, and forming trenches to expose sidewalls of the nanosheet stack. The method also includes forming source/drain (S/D) regions, where forming the S/D regions including forming first portions of the S/D regions on portions of the nano sheet stack, forming second portions of the S/D regions, wherein the first portions are different than the second portions, and replacing the sacrificial gate with a conductive gate material. Also provided are embodiments of a semiconductor device formed by the method described herein.

Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.

Abstract: A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.

Abstract: A method of forming a stacked nanosheet complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device is provided. The method includes forming a plurality of semiconductor layers on a substrate, and patterning the plurality of semiconductor layers to form a plurality of multi-layer nanosheet fins with a fill layer between the multi-layer nanosheet fins and an endwall support on opposite ends of the nanosheet fins. The method further includes reducing the height of the fill layer to expose at least a top three semiconductor nanosheet segments of the multi-layer nanosheet fins, and removing two of the at least top three semiconductor nanosheet segments. The method further includes forming a protective layer on one of the at least top three semiconductor nanosheet segments.

Abstract: A method for removing photoresist bridging defects includes coating a photoresist layer over a dielectric layer formed over a substrate, applying a first developer that results in formation of one or more photoresist bridging defects, and applying a second developer to remove the one or more photoresist bridging defects. The first developer is an aqueous base developer and the second developer is a reverse tone weak developer (RTWD), the RTWD being a mixture of a first (good) solvent and a second (bad) solvent for the photoresist.

Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.

Abstract: A method for removing photoresist bridging defects includes coating a photoresist layer over a dielectric layer formed over a substrate, applying a first developer that results in formation of one or more photoresist bridging defects, and applying a second developer to remove the one or more photoresist bridging defects. The first developer is an aqueous base developer and the second developer is a reverse tone weak developer (RTWD), the RTWD being a mixture of a first (good) solvent and a second (bad) solvent for the photoresist.