Abstract: An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.

Abstract: A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.

Abstract: Peripheral devices for a three-dimensional memory device can be formed over an array of memory stack structures to increase areal efficiency of a semiconductor chip. First contact via structures and first metal lines are formed over an array of memory stack structures and an alternating stack of insulating layers and electrically conductive layers. A semiconductor material layer including a single crystalline semiconductor material or a polycrystalline semiconductor material is formed over first metal lines. After formation of semiconductor devices on or in the semiconductor material layer, metal interconnect structures including second metal lines and additional conductive via structures are formed to electrically connect nodes of the semiconductor devices to respective first metal lines and to memory devices underneath.

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract: A stain-barrier is described along with methods of its application to a fabric. The stain barrier can be applied to fabric samples and limits the amount of fabric with which deposited liquid is able to interact. This stain barrier reduces unwanted variability between samples of different dilution or fabric type so that limits of stain detection can be assigned more accurately and precisely and stain detection techniques can be transparently compared.

Abstract: A stain-barrier is described along with methods of its application to a fabric. The stain barrier reduces variability between samples of different dilution or fabric type so that limits of stain detection can be assigned more accurately and precisely and stain detection techniques can be transparently compared.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: A method of fabricating a memory device is provided. The method includes forming a first alternating stack of insulator layers and spacer material layers over a semiconductor substrate, etching the first alternating stack to expose a single crystalline semiconductor material, forming a first epitaxial semiconductor pedestal on the single crystalline semiconductor material, such that the first epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor material, forming an array of memory stack structures through the first alternating stack, and forming at least one semiconductor device over the first epitaxial semiconductor pedestal.

Abstract: A slurry for polishing a phase change material, such as Ge—Sb—Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at least one of damage to (e.g., scratching of) a polished surface of phase change material, an amount of force to be applied during polishing, and a static etch rate of the phase change material, while optionally providing selectivity for the phase change material over adjacent dielectric materials. A polishing method includes applying a slurry with one or more of the above-noted properties to a phase change material, as well as bringing the polishing pad into frictional contact with the phase change material. Polishing systems are disclosed that include a plurality of sources of solids (e.g., abrasive particles) and provide for selectivity in the solids that are applied to a substrate or polishing pad.

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract: Methods for identifying chemical contrasts on a common surface are generally provided. The presence of a stain on a surface can be detected by applying a testing vapor, such as water, onto the surface and monitoring the surface with an infrared camera that detects wavelengths of about 700 nm to about 1 mm and/or a microbolometer that detects wavelengths of about 7.5 ?m to about 14 ?m. The surface may be at room temperature or preheated during the detection method.

Abstract: An approach is provided for acquiring and integrating data into external services. According to the approach, image and/or video data and identification data are received from a client device. The image and/or video data includes one or more images and/or video data of an object that are acquired by the client device and the identification data is data that uniquely identifies the object. Record data is generated and stored that includes the identification data and at least a reference to the image and/or video data. The image and/or video data and the identification data are transmitted to an external service. This identification data allows an external service to associate the image and/or video data with other data maintained by the external service.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract: An approach is provided for acquiring and integrating data into external services. According to the approach, image and/or video data and identification data are received from a client device. The image and/or video data includes one or more images and/or video data of an object that are acquired by the client device and the identification data is data that uniquely identifies the object. Record data is generated and stored that includes the identification data and at least a reference to the image and/or video data. The image and/or video data and the identification data are transmitted to an external service. This identification data allows an external service to associate the image and/or video data with other data maintained by the external service.