Patents by Inventor Zhichao Zhang
Zhichao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240195637Abstract: A method and device for zero-trust fusion computation of multi-party data is provided, which adopts a chip-level based trusted execution environment (TEE) technique, and by improving a development preparation phase of a fusion computation background and improving a calculation phase, enable fusion computation of multi-party data to be performed in a zero-trust secure running environment, guaranteeing that the data is in a secure state without trusting any party during an entire process of transmission, storage and fusion computation, and allowing for enhanced data privacy protection. The solution brings many advantages in terms of data storage security, data transmission security and data use security as well as universality and performance superiority.Type: ApplicationFiled: September 18, 2023Publication date: June 13, 2024Inventors: Lei ZHANG, Zhichao YAN
-
Publication number: 20240195209Abstract: Disclosed is a control circuit for a relay in an uninterruptible power supply, comprising a plurality of capacitors comprising at least a first capacitor; and a plurality of relays comprising at least a first relay, a second relay, a third relay and a fourth relay, wherein a first terminal of the first relay is connected to a positive electrode of a battery, a second terminal of the first relay is connected to a first terminal of the first capacitor, a first terminal of the second relay is connected to a negative electrode of the battery, a second terminal of the second relay is connected to a second terminal of the first capacitor, a second terminal of the third relay is connected to the second terminal of the first relay, and a second terminal of the fourth relay is connected to the second terminal of the second relay.Type: ApplicationFiled: June 12, 2023Publication date: June 13, 2024Applicant: Vertiv CorporationInventors: Zhichao ZHANG, Wei XU, Ping GONG, Fan TAN, Weihao PENG
-
Publication number: 20240194690Abstract: The disclosure provides display substrate and display panel, and belongs to field of display technology. The display substrate includes base substrate; and gate lines, data lines and sub-pixels on base substrate. Sub-pixels form first pixel groups arranged side by side along first direction and second pixel groups arranged side by side along second direction; first region is between any two adjacent first pixel groups, and second region is between any two adjacent second pixel groups; common electrode line is in at least a portion of the first regions, and common electrode line and data line are in different first regions; and common electrode line includes common electrode line segments and protrusions each coupled between two common electrode line segments, a width of protrusion in any direction is larger than that of common electrode line segment in first direction; and protrusion is in the second region.Type: ApplicationFiled: August 31, 2021Publication date: June 13, 2024Inventors: Qi DENG, Yong ZHANG, Zhichao YANG, Lingfang NIE, Yashuai AN, Longhu HAO, Desheng WANG, Shuanghai WANG
-
Patent number: 12010249Abstract: A method and device for zero-trust fusion computation of multi-party data is provided, which adopts a chip-level based trusted execution environment (TEE) technique, and by improving a development preparation phase of a fusion computation background and improving a calculation phase, enable fusion computation of multi-party data to be performed in a zero-trust secure running environment, guaranteeing that the data is in a secure state without trusting any party during an entire process of transmission, storage and fusion computation, and allowing for enhanced data privacy protection. The solution brings many advantages in terms of data storage security, data transmission security and data use security as well as universality and performance superiority.Type: GrantFiled: September 18, 2023Date of Patent: June 11, 2024Assignee: NANHU LABORATORYInventors: Lei Zhang, Zhichao Yan
-
Patent number: 12007077Abstract: An LED light bulb is provided. The LED light bulb includes a lamp housing, a bulb base, a stem, first and second conductive supports, a driving circuit, and a flexible LED filament. The flexible filament includes two conductive electrodes, a first LED section, a second LED section, and a conductive section. The first LED section is bent in a first space curved shape. The second LED section is bent in a second space curved shape. The conductive section includes a center point of the flexible LED filament. The flexible LED filament is bent in a third space curved shape comprising the first space curved shape and the second space curved shape.Type: GrantFiled: March 24, 2023Date of Patent: June 11, 2024Assignee: ZHEJIANG SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD.Inventors: Tao Jiang, MingBin Wang, Yuexing Li, Zhichao Zhang, Chihshan Yu, Aiming Xiong, Lin Zhou, JunFeng Xu
-
Patent number: 12009612Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.Type: GrantFiled: September 25, 2020Date of Patent: June 11, 2024Assignee: Intel CorporationInventors: Srikant Nekkanty, Steven Klein, Feroz Mohammad, Joe Walczyk, Kuang Liu, Zhichao Zhang
-
Patent number: 12003023Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.Type: GrantFiled: January 26, 2019Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Zhenguo Jiang, Omkar Karhade, Srichaitra Chavali, Zhichao Zhang, Jimin Yao, Stephen Smith, Xiaoqian Li, Robert Sankman
-
Patent number: 11983820Abstract: An information processing method includes: three-dimensional (3D) point information of a 3D point cloud is obtained; a two-dimensional (2D) point cloud image from projection of the 3D point cloud on a horizontal plane is generated based on the 3D point information; and projection coordinates of 3D points comprised in the 3D point cloud in a reference coordinate system of a reference plane graph are determined based on a consistency degree that the 2D point cloud image has with the reference plane graph, where the reference plane graph is used for representing a projection graph with reference coordinates that is obtained through the projection of a target object on the horizontal plane, and the 3D point cloud is used for representing 3D space information of the target object.Type: GrantFiled: December 15, 2021Date of Patent: May 14, 2024Assignee: ZHEJIANG SENSETIME TECHNOLOGY DEVELOPMENT CO., LTDInventors: Youji Feng, Zhichao Ye, Jiacheng Jin, Guofeng Zhang
-
Publication number: 20240151386Abstract: An LED lighting device includes a seat, an optical assembly and a light source. The seat has a baseplate and a sidewall. A chamber is formed between the baseplate and the sidewall. The optical assembly completely covers a light-emitting side of the LED lighting device. The light source is disposed in the chamber of the seat and includes multiple LED arrays. Each LED array includes an LED chip. The optical assembly includes an optical unit. The optical unit includes multiple first optical members and multiple second optical members corresponding to the first optical members. The LED arrays correspond to the first optical members. Each first optical member possesses an effect of light diffusion resulting from its own material property. Each second optical member includes one or more sets of optical walls. Each set of optical walls surrounds one of the first optical members.Type: ApplicationFiled: December 31, 2021Publication date: May 9, 2024Inventors: MINGBIN WANG, ZHICHAO ZHANG, DONGMEI ZHANG, JIFENG XU, TAO JIANG, KUAN LIN
-
Publication number: 20240145007Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Huangpeng Zhang, Zhichao Du, Ke Jiang, Cong Luo, Daesik Song
-
Patent number: 11962213Abstract: Disclosed is a linear motor, including a mover and a stator which cooperate with each other. The mover includes mover iron cores arranged at intervals in a movement direction of the mover, and the stator includes permanent magnets arranged at intervals in the movement direction. Each of the mover iron cores includes an iron core yoke portion and an iron core tooth unit joined to each other. The iron core tooth unit defines an opening, and each of the permanent magnets is located at least partially within the opening.Type: GrantFiled: April 27, 2021Date of Patent: April 16, 2024Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAIInventors: Lei Jiao, Fang Xie, Xi Gao, Weijian Liu, Zhichao Zhang
-
Patent number: 11954592Abstract: The disclosure provides a collaborative deep learning method and a collaborative deep learning apparatus. The method includes: sending an instruction for downloading a global model to a plurality of user terminals; receiving a set of changes from each user terminal; storing the set of changes; recording a hash value of the set of changes into a blockchain; obtaining a storage transaction number from the blockchain for the hash value of the set of changes; sending the set of changes and the storage transaction number to the plurality of user terminals; receiving the set of target user terminals from the blockchain; updating the current parameters of the global model based on sets of changes corresponding to the set of target user terminals; and returning the sending the instruction, to update the global model until the global model meets a preset condition.Type: GrantFiled: September 4, 2020Date of Patent: April 9, 2024Assignee: TSINGHUA UNIVERSITYInventors: Ke Xu, Zhichao Zhang, Bo Wu, Qi Li, Songsong Xu
-
Publication number: 20240111090Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Robert A. May, Tarek Ibrahim, Shriya Seshadri, Kristof Darmawikarta, Hiroki Tanaka, Changhua Liu, Bai Nie, Lilia May, Srinivas Pietambaram, Zhichao Zhang, Duye Ye, Yosuke Kanaoka, Robin McRee
-
Publication number: 20240114233Abstract: A processing method includes obtaining target configuration parameters that include a first configuration parameter for a first function module and a second configuration parameter for a second function module, initializing the first function module based at least on the first configuration parameter, initializing the second function module based at least on the second configuration parameters, and feeding back feedback information indicating completion of initialization after initialization of the first function module is completed and before initialization of the second function module is completed.Type: ApplicationFiled: September 11, 2023Publication date: April 4, 2024Inventors: Shanghui ZHANG, Zhichao CHEN
-
Publication number: 20240104687Abstract: Embodiments of the disclosure provide a method and apparatus for running a service, and an electronic device. An embodiment of the method includes: determining a target deployment manner of a graphics processing unit (GPU) according to performance data of each service in a service set, where the deployment manner includes: dividing the GPU into sub-GPUs of a respective size and determining a service configured to be run by each sub-GPU; and switching, for the service in the service set, running of the service from a sub-GPU indicated by a current deployment manner to a sub-GPU indicated by the target deployment manner. According to the embodiment, waste of the GPU can be reduced by running a plurality of services on the GPU.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Inventors: Zhichao LI, Sikai QI, Zherui LIU, Yibo ZHU, Chuanxiong GUO, Cheng TAN, Jian ZHANG, Jian WANG
-
Patent number: 11942053Abstract: Disclosed are a display panel and a driving method therefor, and a display device. Two adjacent rows of sub-pixels are taken as a row group, and the row group is provided with a first sub row group and a second sub row group that are arranged in a column direction; a gate electrode of a first transistor in the first sub row group is electrically connected to a first gate line; a gate electrode of a second transistor in the second sub row group is electrically connected to a second gate line; two adjacent sub-pixels in the column direction share one third transistor, and a gate electrode of the third transistor in the row group is electrically connected to a third gate line; and the first transistor and the second transistor in one column of sub-pixels are electrically connected to a data line by means of the shared third transistor.Type: GrantFiled: February 20, 2020Date of Patent: March 26, 2024Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xianglei Qin, Jian Lin, Yong Zhang, Limin Zhang, Zepeng Sun, Zhichao Yang, Liangzhen Tang, Zhilong Duan, Honggui Jin, Yashuai An, Lingfang Nie, Jian Wang, Li Tian, Jing Pang, Xuechao Song
-
Patent number: 11927844Abstract: Provided is a display substrate. The display substrate includes: a base substrate including a display region and a non-display region surrounding the display region; a gate drive circuit disposed in the non-display region; a plurality of first signal lines disposed in the peripheral region and connected to the gate drive circuit; and a plurality of second signal lines disposed in the non-display region and connected to the gate drive circuit; wherein each of the first signal line and the second signal line is configured to supply a signal to the gate drive circuit, and a frequency of the signal supplied by the first signal line is lower than a frequency of the signal supplied by the second signal line.Type: GrantFiled: March 9, 2021Date of Patent: March 12, 2024Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Groups Co., Ltd.Inventors: Zepeng Sun, Yong Zhang, Xianglei Qin, Jian Wang, Yanchen Li, Jian Lin, Limin Zhang, Zhichao Yang, Liangzhen Tang, Zhilong Duan, Yashuai An, Lingfang Nie, Honggui Jin, Li Tian
-
Publication number: 20240063544Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.Type: ApplicationFiled: October 31, 2023Publication date: February 22, 2024Applicant: Intel CorporationInventors: Jimin Yao, Robert L. Sankman, Shawna M. Liff, Sri Chaitra Jyotsna Chavali, William J. Lambert, Zhichao Zhang
-
Patent number: 11903138Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.Type: GrantFiled: July 22, 2021Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
-
Patent number: 11885481Abstract: The present invention provides an LED illumination device, including: a light source carrier including a base, an accommodating space formed on the base; a light emitting unit including a light emitter and a lamp board fixed to the light source carrier; and an optical member covering or at least partially covering the light emitting unit. The light emitting unit and the optical member are both disposed in the accommodating space. The optical member includes a first light distribution unit and a second light distribution unit. At least 70% of a luminous flux generated by the light emitter in operation is directly emitted from the LED illumination device through the second light distribution unit.Type: GrantFiled: August 27, 2021Date of Patent: January 30, 2024Assignee: JIAXING SUPER LIGHTING ELECTRIC APPLIANCE CO., LTDInventors: Mingbin Wang, Zhichao Zhang, Tao Jiang, Chen-kun Chen, Dongmei Zhang