Patents by Inventor Zhichao Zhang

Zhichao Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355849
    Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Jimin Yao, Shawna M. Liff, William J. Lambert, Zhichao Zhang, Robert L. Sankman, Sri Chaitra J. Chavali
  • Patent number: 11337972
    Abstract: A pharmaceutical preparation includes a first active component, a second active component and pharmaceutically acceptable excipients. The first active component is at least one selected from the group consisting of a neutral endopeptidase inhibitor and a precursor, an active metabolite, a stereoisomer, a pharmaceutically acceptable salt, a prodrug and a solvate thereof. The second active component is at least one selected from the group consisting of a compound represented by the following formula (I) or a precursor, an active metabolite, a stereoisomer, a pharmaceutically acceptable salt, a prodrug and a solvate thereof. The pharmaceutically acceptable excipients include one or more disintegrants and/or one or more fillers.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 24, 2022
    Assignees: WUHAN LL SCIENCE AND TECHNOLOGY DEVELOPMENT CO., LTD., WUHAN QR PHARMACEUTICALS CO., LTD., WUHAN ZY PHARMACEUTICALS CO., LTD.
    Inventors: Xiaojing Hu, Lina Qian, Zhichao Zhang, Yuanping Wang, Yongkai Chen, Wei Feng, Wenwen Qi, Chaodong Wang
  • Publication number: 20220155539
    Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Inventors: Srinivas V. PIETAMBARAM, Brandon C. MARIN, Sameer PAITAL, Sai VADLAMANI, Rahul N. MANEPALLI, Xiaoqian LI, Suresh V. POTHUKUCHI, Sujit SHARAN, Arnab SARKAR, Omkar KARHADE, Nitin DESHPANDE, Divya PRATAP, Jeremy ECTON, Debendra MALLIK, Ravindranath V. MAHAJAN, Zhichao ZHANG, Kemal AYGÜN, Bai NIE, Kristof DARMAWIKARTA, James E. JAUSSI, Jason M. GAMBA, Bryan K. CASPER, Gang DUAN, Rajesh INTI, Mozhgan MANSURI, Susheel JADHAV, Kenneth BROWN, Ankar AGRAWAL, Priyanka DOBRIYAL
  • Publication number: 20220157706
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 19, 2022
    Inventors: Sujit SHARAN, Kemal AYGUN, Zhiguo QIAN, Yidnekachew MEKONNEN, Zhichao ZHANG, Jianyong XIE
  • Patent number: 11334652
    Abstract: A fingerprint identification method, a device, a mobile terminal, and a storage medium, belong to the technical field of information processing technology. The method is applied to a terminal, response to detecting a touch operation on a specified application icon, obtaining fingerprint information corresponding to the touch operation; transmitting the fingerprint information to an application corresponding to the specified application icon; the application performing a safety authentication to the fingerprint information; and response to determining that the fingerprint information passes the safety authentication, the application entering an application display interface.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 17, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Zhichao Zhang
  • Patent number: 11329358
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Patent number: 11314391
    Abstract: The present application provides a navigation bar controlling method and device, and relates to the field of human-computer interaction. The method includes displaying a navigation bar, the navigation bar comprising at least one virtual button; starting an application; and displaying at least one function control on the navigation bar according to the running application, wherein the at least one function control is configured to trigger at least one target function of the application. The present application dynamically adds the display of at least one function control on the navigation bar according to the running application, and the at least one function control is configured to trigger the at least one target function of the application. The navigation bar enhances the function of the navigation bar on the basis of the virtual buttons provided natively, with the entry of other functions dynamically provided by the running application.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 26, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Zhichao Zhang, Guojun Sun
  • Publication number: 20220123629
    Abstract: The present disclosure discloses a combined cooling system for a motor and a motor controller, which comprises a water cooling assembly, an oil cooling assembly, and an oil-water heat exchanger; one end of the water cooling assembly is connected to an cooling water outlet of the motor, the other end is connected to an cooling water inlet of the motor controller and/or a water inlet of the oil-water heat exchanger; one end of the oil cooling assembly is connected to a cooling oil outlet of the motor, the other end of the oil cooling assembly is connected to an oil inlet of the oil-water heat exchanger, and an oil outlet of the oil-water heat exchanger is connected to a cooling oil inlet of the motor.
    Type: Application
    Filed: June 30, 2021
    Publication date: April 21, 2022
    Inventors: Kuizhu Shao, Zhichao Zhang, Yu Duan, Jinhe Xu
  • Publication number: 20220102892
    Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Srikant Nekkanty, Steven Klein, Feroz Mohammad, Joe Walczyk, Kuang Liu, Zhichao Zhang
  • Patent number: 11291133
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gregorio R. Murtagian, Kuang C Liu, Kemal Aygun
  • Patent number: 11282633
    Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Fay Hua, Sidharth Dalmia, Zhichao Zhang
  • Patent number: 11276635
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Sujit Sharan, Kemal Aygun, Zhiguo Qian, Yidnekachew Mekonnen, Zhichao Zhang, Jianyong Xie
  • Publication number: 20220037803
    Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 3, 2022
    Inventors: Zhichao Zhang, Jiwei Sun, Kemal Aygun
  • Patent number: 11230817
    Abstract: The present invention discloses a rainfall sensing two-component high-polymer grouting device and a manufacturing method therefor, and belongs to the technical field of soil protection. The present invention includes an iron box and a water bucket. The water bucket is slidably fitted in the iron box. An inner bottom of the iron box is provided with a pair of lever upturning apparatuses symmetrically distributed about an axis center of the iron box. A lower surface of the iron box is provided with a curing agent ejector and a resin ejector. An end of two lever upturning apparatuses is slidably connected to a low surface of the water bucket. The switches of the curing agent ejector and the resin ejector are respectively connected to the other end of a lever upturning apparatus. A peripheral surface of the water bucket is provided with a permeable hole, and a permeable head is installed on the permeable hole.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 25, 2022
    Inventors: Changguang Qi, Zhichao Zhang, Jinjing Pan, Kan Liu, Longzhen Ye, You Gao
  • Patent number: 11212932
    Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Srikant Nekkanty, Zhichao Zhang, Kemal Aygun
  • Publication number: 20210381657
    Abstract: This application relates to the field of lighting, and discloses an LED filament including: at least one LED section, each LED section including at least two LED chips, adjacent LED chips being electrically connected to each other; electrodes, electrically connected to the LED section; and a light conversion layer, wrapping the LED section and parts of the electrodes, and including a top layer and a carrying layer, the carrying layer including a base layer and a transparent layer, the base layer including an upper surface and a lower surface opposite to each other, the upper surface of the base layer being in contact with a part of the top layer, and a part of the lower surface of the base layer being in contact with the transparent layer. This application has the characteristics of uniform light emission and good heat dissipation effect.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Inventors: AIMING XIONG, LIN ZHOU, MINGBIN WANG, CHENKUN CHEN, CHIHSHAN YU, TAO JIANG, YUEXING LI, HAYATO UNAGIIKE, YUKIHIRO SAITO, ZHICHAO ZHANG
  • Publication number: 20210354086
    Abstract: A method for simultaneously removing high-load sulfur dioxide and nitrogen oxide in waste gas, relating to the technical field of industrial waste gas purification by biological methods. According to the method, the waste gas is led into a simultaneous desulfurization and denitrification packing tower and removed, microbial floras for simultaneously removing the sulfur dioxide and the nitrogen oxide are loaded on fillers of the packing tower, and the molar concentration ratio of the sulfur dioxide to the nitrogen oxide in the waste gas is (0.76˜1.06):1.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Kan LI, Xuxiang ZHANG, Hongqiang REN, Peishi SUN, Zhichao ZHANG
  • Publication number: 20210351116
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Publication number: 20210352807
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • Publication number: 20210344116
    Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Applicant: Intel Corporation
    Inventors: Sidharth Dalmia, Trang Thai, William James Lambert, Zhichao Zhang, Jiwei Sun